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SDRAM
Austin Semiconductor, Inc. 4 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
* * * * * * * * * * * * * Extended Testing Over -55C to +125 C and Industrial Temp -40C to 85 C WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge and Auto Refresh Modes Self Refresh Mode (Industrial, -40C to 85 C only) 4,096-cycle refresh LVTTL-compatible inputs and outputs Single +3.3V 0.3V power supply Longer lead TSOP for improved reliability (OCPL*) Short Flow / Long Flow Test Screening Options
AS4SD4M16
PIN ASSIGNMENT (Top View)
54-Pin TSOP
OPTIONS
* *
MARKING
4M16 No. 901
Note: "\" indicates an active low.
Configurations 4 Meg x 16 (1 Meg x 16 x 4 banks) Plastic Package - OCPL* 54-pin TSOP (400 mil) DG Timing (Cycle Time) 8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns) 10ns; tAC = 9ns @ CL = 2 Operating Temperature Ranges -Military (-55C to +125 C) -Industrial Temp (-40C to 85 C)
*
-8 -10
*
XT IT
4 Meg x 16 Configuration 1 Meg x 16 x 4 banks Refresh Count 4K Row Addressing 4K (A0-A11) Bank Addressing 4 (BA0, BA1) Column Addressing 256 (A0-A7)
KEY TIMING PARAMETERS
SPEED GRADE -8 -10 -8 -10 CLOCK ACCESS TIME FREQUENCY CL = 2** CL = 3** 125 MHz - 6.5ns 100 MHz - 7ns 83 MHz 9ns - 66 MHz 9ns - SETUP TIME 2ns 3ns 2ns 3ns HOLD TIME 1ns 1ns 1ns 1ns
*Off-center parting line **CL = CAS (READ) latency
For more products and information please visit our web site at www.austinsemiconductor.com
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SDRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 6,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
AS4SD4M16
AS4SD4M16 Rev. 1.5 10/01
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2
SDRAM
Austin Semiconductor, Inc.
TABLE OF CONTENTS
Functional Block Diagram - 4 Meg x 16 ........................................ 4 Pin Descriptions ............................................................................. 5 Functional Description ................................................................. 6 Initialization ............................................................................. 6 Register Definition ................................................................. 6 Mode Register ................................................................ 6 Burst Length ................................................................... 6 Burst Type ....................................................................... 7 CAS Latency ................................................................... 8 Operating Mode ............................................................. 8 Write Burst Mode .......................................................... 8 Commands ....................................................................................... 9 Truth Table 1 (Commands and DQM Operation) ......................... 9 Command Inhibit .................................................................... 10 No Operation (NOP) .................................................................10 Load Mode Register ............................................................. 10 Active ....................................................................................... 10 Read .......................................................................................... 10 Write ......................................................................................... 10 Precharge ................................................................................. 10 Auto Precharge ...................................................................... 10 Burst Terminate ...................................................................... 11 Auto Refresh .......................................................................... 11 Self Refresh ............................................................................. 11 Operation ..................................................................................... 12 Bank/Row Activation ............................................................ 12 Reads ........................................................................................ 13 Writes ....................................................................................... 19 Precharge................................................................................... 21 Power-Down...............................................................................21 Clock Suspend......................................................................... 22 Burst Read/Single Write ...........................................................22 Concurrent Auto Precharge ................................................. 23
Truth Table 2 (CKE) ......................................................................25 Truth Table 3 (Current State, Same Bank) ................................. 26 Truth Table 4 (Current State, Different Bank) ........................... 28
AS4SD4M16
Absolute Maximum Ratings ........................................................ 30 DC Electrical Characteristics and Operating Conditions......... 30 ICC Specifications and Conditions .............................................. 30 Capacitance ..................................................................................... 31 AC Electrical Characteristics (Timing Table) ............................31 Timing Waveforms Initialize and Load Mode Register ..................................... 34 Power-Down Mode ................................................................ 35 Clock Suspend Mode ........................................................... 36 Auto Refresh Mode .............................................................. 37 Self Refresh Mode ................................................................. 38 Reads Read - Without Auto Precharge ................................. 39 Read - With Auto Precharge ....................................... 40 Alternating Bank Read Accesses .............................. 41 Read - Full-Page Burst ......................................................... 42 Read - DQM Operation ................................................ 43 Writes Write - Without Auto Precharge ................................ 44 Write - With Auto Precharge ...................................... 45 Alternating Bank Write Accesses .............................. 46 Write - Full-Page Burst ................................................. 47 Write - DQM Operation ............................................... 48
AS4SD4M16 Rev. 1.5 10/01
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SDRAM
Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM 4 Meg x 16 SDRAM
AS4SD4M16
CKE CLK CS\ WE\ CAS\ RAS\
CONTROL LOGIC
COMMAND DECODE
BANK1
BANK2 BANK3
MODE REGISTER
REFRESH 12 COUNTER
12
1 2
ROW ADDRESS MUX
12
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK 0 MEMORY ARRAY (4,096 X 256 X 16)
SENSE AMPLIFIERS 4096
2
2
DQML, DQMH
16
DATA OUTPUT REGISTER
16
DQ0-DQ15
2
A0, A10, BA
14
ADDRESS REGISTER
2
BANK CONTROL LOGIC
I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 256 (X16) COLUMN DECODER
16
DATA INPUT REGISTER
8
COLUMNADDRESS COUNTER/ LATCH
8
AS4SD4M16 Rev. 1.5 10/01
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SDRAM
Austin Semiconductor, Inc.
PIN DESCRIPTION
TSOP PIN NUMBERS 38 SYMBOL CLK TYPE
DESCRIPTION
AS4SD4M16
Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.
37
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS\ enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS\ is registered HIGH. CS\ provides for external bank selection on systems with multiple banks. CS\ is considered part of the command code. Command Inputs: RAS\, CAS\, and WE\ (along with CS\) define the command being entered. Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: A0-A11 are sampled during the ACTIVE command (row address A0-A11) and READ/WRITE command (column address A0-A7, with A10 defining AUTO PRECHARGE) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0,BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command.
19
CS\
Input
16, 17 18 15, 39
WE\, CAS\ RAS\ DQML, DQMH
Input
Input
20, 21 23-26, 29-34, 22, 35
BA0, BA1 A0-A11
Input Input
2, 4, 5, 7, 8 10, 11, 13, 42 44, 45, 47, 48 50, 51, 53 36, 40 3, 9, 43, 49 6, 12, 46, 52 1, 14, 27 28, 41, 54
AS4SD4M16 Rev. 1.5 10/01
DQ0- DQ15
Input/ Data I/O: Data bus. Output
NC VDDQ VSSQ VDD VSS
-- Supply Supply Supply Supply
No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: +3.3V 0.3V. Ground.
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5
SDRAM
Austin Semiconductor, Inc.
FUNCTIONAL DESCRIPTION
In general, the 64Mb SDRAM is quad-bank DRAM (1 Meg x 16 x 4 banks) which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits ( x16: A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initalization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable, the SDRAM requires a 100s delay prior to applying an executable command. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command.
AS4SD4M16
REGISTER DEFINITION
Mode Register The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 (x16) when the burst length is set to two; A2-A7 (x16) when the burst length is set to four; and by A3-A7 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
AS4SD4M16 Rev. 1.5 10/01
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SDRAM
Austin Semiconductor, Inc.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
Burst Length 2
AS4SD4M16
Table 1 BURST DEFINITION
Starting Column Address A0 0 1 A0 A1 0 0 0 1 1 0 1 1 A0 A2 A1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0 - A9 location 0 - y Order of Access Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5, 7,0,1,2,3,4,5,6 Cn, Cn+1, Cn+2, Cn+3, Cn+4... ...Cn-1, Cn... 0-1 1-0 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Not Supported
4
8
Full Page (y)
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Mode Register(Mx) 11 10 Reserved* 9 WB 8 7 Op Mode 6 5 4 CAS Latency 3 BT 2 1 0 Burst Length
* Should program M11, M10=0,0 to ensure compatibility with future devices.
M2 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1
M0 0 1 0 1 0 1 0 1
Burst Length M3=0 M3=1 1 1 2 2 4 4 8 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
M3 0 1
Burst Type Sequential Interleave
M6 0 0 0 0 1 1 1 1
M5 0 0 1 1 0 0 1 1
M4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
M8 0 -
M7 0 -
M6 - M0 Defined -
Operating Mode Standard Operation All other states reserved
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
FIGURE 1 MODE REGISTER DEFINITION
NOTE: 1. For full-page accesses: y = 256 (x16). 2. For a burst length of two, A1-A7 (x16) select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7 (x16) select the block-of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7 (x16) select the clock-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A7 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 (x16) select the unique column to be accessed, and Mode Register bit M3 is ignored.
AS4SD4M16 Rev. 1.5 10/01
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7
SDRAM
Austin Semiconductor, Inc.
CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used.
AS4SD4M16
Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
T0
CLK
T1
321 321 321 321 321 321 321 321
T2
321 321 321 321
T3
Table 2
CAS LATENCY
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED CAS LATENCY = 2 CAS LATENCY = 3
COMMAMD DQ
DOUT
tAC
CAS Latency = 2
T0
CLK
T1
T2
COMMAMD
READ
NOP
NOP tLZ
NOP tOH DOUT
DQ
tAC
CAS Latency = 3
UNDEFINED DON'T CARE
Figure 2 CAS LATENCY
AS4SD4M16 Rev. 1.5 10/01
8
4321 4321 4321 4321 4321
321 321 321 321
321 321 321
321 321 321
311121 342 2231 331121 1122 3231 242 311121 1231 2231 332111 242 311121 342 243
321 321 321 321 321
321 321 321 321
32321 1 321 2121 3332 1 31 21 22211 33321 2221 3132 11 1 22211 33321
321 321 321 321
321 321 321 321
54321 21 54321 54321 54321
3211 21 32 21 3321 32 3321 21 3211 21
READ
NOP tLZ
NOP tOH
-8 -10
83 66
125 100
T3
T4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SDRAM
Austin Semiconductor, Inc.
COMMANDS
Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Two additional Truth Tables appear following the Operation section; these tables provide current state/next state information.
AS4SD4M16
TRUTH TABLE 1- Commands and DMQ Operation
(Note: 1) NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (select bank and activate row) READ (select bank and column and start READ burst) WRITE (select bank and column and start WRITE burst) BURST TERMINATE PRECHARGE (deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z CS\ H L L L L L L L L RAS\ X H L H H H L L L CAS\ X H H L L H H L L WE\ DQM X X H X H X H X L X L X L X H L X X L H ADDR DQs NOTES X X X X Bank/Row X 3 Bank/Col X 4 Bank/Col Valid 4 X Active Code X 5 X OpCode X X Active High-Z 6,7 2 8 8
NOTE:
1. 2. 3. 4. 5. 6. 7. 8. CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the Mode Register. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
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SDRAM
Austin Semiconductor, Inc.
COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS\ is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-A11. See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 (x16) selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 (x16) selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.
AS4SD4M16
AS4SD4M16 Rev. 1.5 10/01
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SDRAM
Austin Semiconductor, Inc.
BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS\-BEFORE-RAS\ (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms *(tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625s/3.906s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC), once every 64ms/ 16ms.
AS4SD4M16
SELF REFRESH (Industrial -40C to +85C Only) The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care," with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR, because time is required for the completion of any internal refresh in progress. If during normal operation AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. The self refresh option is not available for the -55 to +125 screening option.
*64ms for -40 to +85 C ( Industrial Temperatures) and 16ms for -55 to +125C (Military Temperatures)
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SDRAM
Austin Semiconductor, Inc.
OPERATION
BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 30ns with a 90 MHz clock (11.11ns period) results in 2.7 clocks, rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/ tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
AS4SD4M16
CLK
CKE CS\ RAS\ CAS\ WE\
HIGH
A0-A11 BA0, 1
ROW ADDRESS BANK ADDRESS
Figure 3 ACTIVATING A SPECIFIC ROW IN A SPECIFIC BANK
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
NOP
READ or WRITE
t RCD
DON'T CARE
Figure 4 EXAMPLE: MEETING tRCD (MIN) WHEN 2AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
22109876543221 3 31 31109876543211 22 32 1 21109876543321 31 2 21 321 22 3 3110987654321 22 31 31109876543221 2109876543311 22 987654321 9 1 987654321 9876 1 18765432654321 98765987154321 4321 1 9 9871 6 1 98765432154321 9876 1 18765432654321 98765987154321 4321 21 541 23 21 21098765454121 210987654321 323 23 21098765454121 32121 21098765432121 21 23 543 21098765432121 543 21098765454121 321
4321 4321 4321
54321 54321 54321 54321 54321
432143210987654321 215 6 1 436543210987654321 225 1 432143210987654321 211 6 4321 21 6 432543210987654321 265 15 432143210987654321 6143210987654321 654321 5 1 654543210987654321 143 3 654121210987654321 321210987654321 543 654143 143 3 5 1 654521210987654321 3 1 654121210987654321 321210987654321 543 987654110 1 3 1 2 1 987654221987654321 310 987654121987654321 321987654321 210 2 1 987652121987654321 4110 310 987652221987654321 4310 987654321987654321 2 54321 54321 54321 54321 54321
54321 54321 54321 54321 54321
54321 54321 54321 54321 54321
4321 21 21 4321 4321 21 4321 4321
SDRAM
Austin Semiconductor, Inc.
READs
READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command, and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting.
AS4SD4M16
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of alonger burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one.
T0 CLK CLK
T1
T2
T3
CKE CS\ RAS\ CAS\ WE\ A0-A7: x16 A8, A9, A11: x16 A10
HIGH
COMMAND
READ
NOP
NOP tOH
DOUT
DQ
tAC
CAS Latency = 2
T0 CLK
T1
T2
T3
COLUMN ADDRESS
ENABLE AUTO PRECHARGE
COMMAND
READ
NOP
NOP
NOP
DISABLE AUTO PRECHARGE
BANK ADDRESS
DOUT
CAS Latency = 3
Figure 5 READ COMMAND
Figure 6 CAS LATENCY
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
321 321 321 321
BA0, 1
DQ
tAC
4321 4321 4321 4321
4321 4321 4321 4321
7654321 7654321 7654321 7654321
tLZ
t OH
321 321 321
4321 4321 4321 4321
T4 DON'T CARE UNDEFINED
321 321 321
7654321 7654321 7654321 7654321
tLZ
321 321 321 321
321 321 321 321
321 321 321
321 321 321 321
4321 4321 4321
321 321 321 21 321
321 21 321 321
1 22 1 3243210987654321 21 4 1 1 1098765434121 1098765434321 231 3213210987654321 1098765434321 211 2 3243210987654321 1 211 4 1098765434321 411 2 3213210987654321 24 1 1 1098765432121 231 2 3213210987654321 1098765434321 1 2 3243210987654321 1 1098765434321876543321243210987654321 211321 21 213 1 1098765434321876543321243210987654321 1 211321 21 21321 11 1 1098765434321 211 2 3213210987654321 4 1 1 431 21 2 321 24 1 1 1 1098765434321 1098765432121 21 3243210987654321 213210987654321 1 1 8 31 821 1 654321 1 3 31 1 1 8765437654321 1 6543210987654321 121 1 1 1765487654321 8 32654321 21 1 6543210987654321 12109 1765487654321 8765432187654321 0 321 1 1 1 0987654321 8765432187654321 109 109 1 1987654654321 0987654654321 321 8765432187654321 10987654321 1 87654321 1 54321 1 1 8 31 3 1 87654321 5432210987654321 1 32 1 1765487654321 8765487654321 321 21 5432110987654321 11 3210987654321 1987654654321 0 321 8765410987654321 109 321 1987654654321 0 321 8765432187654321
4321 4321 4321 4321

7654321654654 7 4 7654 4 76543216543213216543213217654321321 7654 7 7654 7651 76543216543213216543213217654321321 73213216543213217654321321 621 7 7651 54 7 7654 7654 76543216543213216543213217654321321 7654 7 7654 654 654 765 76543216543213216543213217654321321 7321 7 7321 4324 7654 76543216543213216543213217654321321 7354 7 7324 6 65 4321 7654

765435 6 432 4432 321 7654331321657654321657654321 424 654 43211 431 2 43211 7654321121657654321657654321 621121657654321657654321 523 43 43211 43211 432 432 7654432321657654321657654321 3323 632 43211 432 321 43211 432 321 7654421121657432121657432121 3211 654 46543 432 46543 432 7654421321657654321657654321 3541 454 632 43211 43211

6543217654321321654321321 7654 7 654 6543217654324 735 6 654 6543217654321321654321321 7321321654321321 621 7 321 54 7 321 654 6543217654321321654321321 7651 7 654 4 654 6543217654321321654321321 7321 7 321 654

7654321321654421327657654321 7654 7 7354 1 43 6 765435 76 6321 54 321 2 7654321321654421127657654321 7321321654432321657354321 321 7 73213 7 4621 624 7 7332 1 4321 54 654 321 7654321321654332121657654321 7651 7 73323 1 4321 654 4 654 1 7654321321654421127657654321 7321 7 74211 7 4321 6543 321

This is shown in Figure 7 for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can
AS4SD4M16 Rev. 1.5 10/01

COMMAND
ADDRESS
COMMAND
ADDRESS
CLK
DQ
NOTE: Each READ command may be to either bank. DQM is LOW.
CLK
DQ
Austin Semiconductor, Inc.
BANK, COL n
READ
T0
BANK, COL n
READ
T0
CAS Latency = 3
NOP
T1
CAS Latency = 2
Figure 7 CONSECUTIVE READ BURSTS
NOP T1 NOP T2 NOP T2 DOUT n NOP T3 DOUT n
14
be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank.
NOP T3 DOUT n+1
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
BANK, COL b
T4
READ
DOUT n+1
BANK, COL b
T4
READ
DOUT n+2
X=2 cycle
X=1 cycle
T5
NOP
DOUT n+2
T5
NOP
DOUT n+3
T6
NOP
DOUT n+3
AS4SD4M16
T6
NOP
SDRAM
DOUT b
T7
NOP
DOUT b
DON'T CARE

SDRAM
Austin Semiconductor, Inc.
AS4SD4M16
T0
T1
T2
T3
T4
T5
CLK

COMMAND
READ

READ

READ

READ

NOP

NOP

ADDRESS
BANK, COL n

BANK, COL a

BANK, COL x

BANK, COL m

DQ
DOUT n

DOUT a

DOUT x

CAS Latency = 2

T0
T1
T2
T3
T4
CLK

COMMAND
READ

READ

READ

READ

NOP

ADDRESS
BANK, COL n

BANK, COL a

BANK, COL x

BANK, COL m

DQ
DOUT n
DOUT a
DOUT x

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.
Figure 8 RANDOM READ ACCESSES
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
654321654334 45 6 654 6543 65432165442112165432132165432121 3323 7 7321 7 4321 6213 7 7654 7 6543 52 4 654 6543 65432165442112165432132165432121 33212165432132165432121 6543 7 7321 7 4321 65432165442112165432132165432121 3323 7 7321 7 4321 654 654 6543 65432165432112165432132165432121 4323 7 7654 7 6543 654

432 4321 4321 1 4321
654321654334 6 43 45 65432165432112165432121 62112165432121 523 7 6521 43 7 6543 65432165442112165432121 332 632 5 65432165443212165432121 3213 7 6321 654 543 65432165442112165432121 4543 7 6343 3323 7 6321 654 543

DOUT m
T5
T6
NOP
NOP
DOUT m
DON'T CARE
SDRAM
Austin Semiconductor, Inc.
Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed.
T0 CLK

AS4SD4M16
T1 T2 T3 T4
DQM
COMMAND
READ

NOP

NOP

NOP

WRITE

ADDRESS

tHZ

tCK
BANK, COL n
BANK, COL b
DQ
DOUT n

DIN b
t DS

NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a CAS latency of one is used, the DQM is not required.
Figure 9 READ TO WRITE
T0
CLK
T1
T2
T3
T4
T5

DQM

COMMAND
READ

NOP

NOP

NOP

NOP

WRITE

ADDRESS

tHZ

DQ
DOUT n

BANK, COL n
BANK, COL b
DIN b

t DS NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank.

DON'T CARE
Figure 10 READ TO WRITE WITH EXTRA CLOCK CYCLE
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
654321 654321 654321 654321

654321 654321 654321 654321
65432111543213215432121 5322 43 621 6 6321 54 543 65433211543213215432121 5322 43 654 6 6323 54 543 65432111543213215432121 5212 43 621 6 6321 543 65432111543213215432121 5322 43 621 6 6541 54

321 321 321
5432121543212154541215434321 543 6 541 6 543 6 321 43 543 321 321 5432121543212154543215434321 543 6 543 6 321 6 521 5432121543212154321215454321 521 6 343 6 323 6 521 5432121543212154323215454321 543 6 523 6 541 6 321
54321 54321 54321 54321

4321 4321 4321 4321
SDRAM
Austin Semiconductor, Inc.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated), and a full-page burst maybe truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last
AS4SD4M16
desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst
T0
T1
T2
T3
T4
T5
t RP
T6
T7
CLK

X = 1 cycles
ADDRESS DQ
BANK a, COL n

BANK (a or all)

BANK a, ROW

T0
T1
T2
T3
T4
T5
t RP
T6
T7
CLK

CAS Latency = 2

DOUT n
DOUT n+1
DOUT n+2
DOUT n+3

COMMAND
READ

NOP

NOP

NOP

PRECHARGE

NOP

NOP

ACTIVE

ADDRESS
BANK a, COL n

BANK (a or all)

BANK a, ROW

DQ

NOTE: DQM is LOW.
Figure 11 READ TO PRECHARGE
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
4321 4321 4321
CAS Latency = 3

DOUT n
DOUT n+1
DOUT n+2
DOUT n+3

DON'T CARE
7654321 7654321 7654321 7654321 7654321
7654321216543214321 6543 765 7654543 6 4324 3214 765 7654321216544321321 6321216543211321 543 3324 765 7654321216544211321 6321 543 765 7654321216543211321 6543 4324 765
X = 2 cycles

7654321 7654321 7654321 7654321 7654321
7654321321654321321 7654 7 7654 7654321321654321321 7321 7 7321 654 654 7654321321654321321 7321 7 7321 654 654 7654321321654321321 7654 7 7654 654 7654321321654321321 7321 7 7654
7654321321 7654 7654654 7 4321 432 4321 31 7654321321657654121657624321 7321321657654321657654321 654 44323 432 3211 4351 7654321321657654321657654321 7321 654 43211 4321 2 7654321321657654321657654321 7654 44321 321 4321
765432132165432132765654321 7654 7 7654 1 4321 765432132165432132765432121 7321 7 7321 1 4321 654 324 654 4321 765432132165432132765654321 7321 7 7651 1 6543 654 4321 765432132165432132765432121 7654 7 7654 1 6543 654 4321 765432132165432132765654321 7654 7 7321 1 4321

COMMAND
READ
NOP
NOP
NOP

PRECHARGE
NOP

NOP
ACTIVE
SDRAM
Austin Semiconductor, Inc.
with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts
AS4SD4M16
may be truncated with a BURST TERMINATE command, provided that AUTO PRECHARGE was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.
T0
T1
T2
T3
T4
T5
T6
CLK

COMMAND
READ

NOP

NOP

NOP

BURST TERMINATE

NOP
NOP

ADDRESS DQ
BANK, COL n

DOUT n

CAS Latency = 2

T0
T1
T2
T3
T4
T5
T6
DOUT n+1
DOUT n+2
DOUT n+3

CLK

COMMAND ADDRESS DQ
READ

NOP

NOP

NOP

BANK, COL n

DOUT n
DOUT n+1

CAS Latency = 3

DOUT n+2
DOUT n+3

NOTE: DQM is LOW.
AS4SD4M16 Rev. 1.5 10/01
654321654354 76 543 654 32 7654 654 4321 44321 73213 432 321 654 65432165432132165432121654332321765432132165432132165432121654321121 732132165432121654321321765432132165432132165654321657432321 621 7 6321 54 7 6543 6213 541 7321 7 7321 7 6543 654 7 7654 7 4321 46541 65432165432132165432121654321121765432132165432132165632321657654321 7654 7 6543 6321 54 7654 7 7654 7 4541 65432165432132165432121654321121765432132165432132165654321657654321 7321 7 6321 654 543 6323 54 7321 7 7321 7 4321 654 654 4321 43211 432

X = 2 cycles
BURST TERMINATE
NOP
NOP

Figure 12 TERMINATING A READ BURST
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
4321 4321 4321
654321654334 6 65 634 5 7654 7 6323 54 41 4321 7654 45 434 654321654321121654321121654331121765432132165654321657654321 621121654332121654322121765432132165432121654321321 523 43 6213 523 4 6213 523 4 7621 7 4541 321 654321654432121654432121654331121765432132165432121654321321 332 654 354 6 6223 54 7354 7 4321 6 4541 32 4321 7654 321 654321654421121654421121654332121765432132165632321657654321 4323 3213 654 4323 3213 654 6213 54 7321 7 6543 654

X = 1 cycles

T7
NOP
DON'T CARE
SDRAM
Austin Semiconductor, Inc.
WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the WRITE command, and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, AUTO PRECHARGE is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 14). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 15. Data n + 1 is either
AS4SD4M16
the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each subsequent WRITE may be performed to a different bank.
T0
T1
T2
T3
CLK

COMMAND ADDRESS DQ
WRITE

NOP

NOP

NOP

BANK, COL n

DIN n

NOTE: Burst length = 2. DQM is LOW.
Figure 14 WRITE BURST
CLK
T0
CLK
CKE CS\ RAS\ CAS\ WE\ A0-A7: x16 A8, A9, A11: x16 HIGH

COMMAND ADDRESS DQ
WRITE

NOP

WRITE

BANK, COL n

BANK, COL b DIN b

COLUMN ADDRESS
NOTE: DQM is LOW. Each WRITE command may be to any bank.
DIN n
DIN n+1
DON'T CARE
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE BANK ADDRESS
Figure 15 WRITE TO WRITE
BA0,1
Figure 13 WRITE COMMAND
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
654321 654321 654321 654321
4321 4321 4321 4321
654654 654 654321321 321321 654321321 321 654 654321321 321 654

656541 6 543 432 54 656321215432121 4323215432121 543 6 323 654541215432121 4321 6 321 6321 6 321 321 543 1 543 3 656323215432121 541 6 654 6 4543 6 6543 321 321 6543215465432156543215432121 65432132154321215432121 6 6321 6 6543 6543215432132154521215432121 6 321 6 4343 6 6321 651 521 543 6543215432432156343215432121 6 651 6 6321 6 6321 324 543

DIN n+1

T1

T2
1 2 21 31 21 3213210987654321 24 1 5 1 1 1109876543221 2109876543321 21 3543210987654321 14 51 1109876543321 2 21 3213210987654321 1 1109876543321 2 21 3213210987654321 1 54 1 2 21 21 321 1 54 1 2109876543321 109876543321 21 3213210987654321 543210987654321 1 2 21 91 21 21 21 21 1 3235 1 1 11098765433219876543321213210987654321 21098765433212876543213543210987654321 21321 21321 21121 14 1 2 21 31 3243210987654321 1 5 1 1109876543221 2109876543321 21 3213210987654321 14 51 1109876543321 2 21 3213210987654321 54 1 1 0 3221 1 8765432187654321 1 109 321 1 1987654654321 0987654652121 3243 1 8765410987654321 109 1987654654321 0 3221 1 8765432187654321 1098765432121 321 543 8765410987654321 109 321 1098765454321 8765432187654321 1 8 321 871 1 5432110987654321 21 43 32 1 1765432654321 8765487654321 5443210987654321 212 431 1765487654321 8 321 1 5432110987654321 212 1 1 54321 21 87654321876 321 1 10987654521 1098765432121 343 21 8765410987654321 1 109 309 54321 1 1 1098765454321 1 8765432187654321 121
SDRAM
Austin Semiconductor, Inc.
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a subsequent READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 17. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The Auto Precharge mode requires a tWR of at least one clock plus time (8ns), regardless of frequency. In addition, when truncating a
AS4SD4M16
WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
T0 CLK
T1
T2
T3 CLK
T0
T1
T2
T3
T4
T5
T6

DQM
COMMAND
ADDRESS
BANK, COL n

BANK, COL a

BANK, COL x

BANK, COL m

WRITE

NOP

NOP

PRECHARGE

NOP

NOP

ADDRESS
NOTE: Each WRITE command may be to any bank. DQM is LOW.
BANK a, COL n

DQ
DIN n

Figure 16 RANDOM WRITE CYCLES

NOTE: DQM coulc remain LOW in this example if the WRITE burst is a fixed length of 2.
T0
CLK
T1
T2
T3
T4
T5
Figure 18 WRITE TO PRECHARGE

COMMAND
WRITE

NOP

READ

NOP

NOP

NOP

ADDRESS
BANK, COL n

DQ
DIN n

NOTE: The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 17 WRITE TO READ
AS4SD4M16 Rev. 1.5 10/01
5432121543211 4321 1 4321 6543 6 5432 21 321 5654326554321 56543 1 4432 4321 21 321 321 5654326554321 432121543211 21 6 5321 54321 5422 543 63 32 21 21 43 6554321 4321 5321 321 321 432 5432154321154322215654321 654321154321215652121 5421 31 2 5412 6521 33 431 4321 6554321 4321 5432154321154321115432121 6 5421 32 5321 4343 32 6543211 4321 5432154321154321215654321 6 5432 5431 4321 6554321
BANK, COL b

DIN n+1

DOUT b

DOUT b+1

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
4321 4321 4321
4321213322145432132121432121 3 42 32 21 43 21 21 43 43 3314 211 321 4 21 5 21 4322 43 43 43 4321213431145432132121432121 3324 322 543 4 21 5 21 41113211143212132121432121 214 432 321 4 43 5 43 4321 44311454321 321 321 22 21 43212144321 21 5 321 43 321 4321 43211432121 322 321 432 543 43212143211 43 5 421 4321 44311454321 43212144321 43 5 332
DQ
DIN n

DIN a

DIN x

DIN m

BANK (a or all)

t WR

DIN n+1

4321 4321 4321

COMMAND
WRITE

WRITE

WRITE

WRITE

t
WR= 2 CLK ("A2 version")

54321 54321 54321
tRP
ACTIVE

BANK a, ROW

DON'T CARE

SDRAM
Austin Semiconductor, Inc.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 19, where data n is the last desired data element of a longer burst.
AS4SD4M16
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
T0
T1
T2
CLK

POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms/16ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS).
COMMAND ADDRESS DQ
NOTE: DQMs is LOW.
WRITE

BURST TERMINATE

NEXT COMMAND
BANK, COL n

DIN n

(DATA)

Figure 19 TERMINATING A WRITE BURST
CLK
CKE CS\
HIGH
RAS\
CAS\ WE\ A0-A9 A10
ALL BANKS
COMMAND
NOP
NOP
ACTIVE
BANK SELECTED
BANK ADDRESS
All banks idle
Input buffers gated off Enter power-down mode. Exit power-down mode.
BA
Figure 20 PRECHARGE COMMAND
1
Figure 21 POWER-DOWN
DON'T CARE
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
21
4321 4321 4321 4321 4321 4321
4321 4321 4321 4321
4321 4321 4321 4321 4321 4321
87654 54321 87654 8765876543210987687654321 8321 476543210987687654321 54321321 87654321 8321 4321 54321 8765476543210987687654321 8321 54321 8765476543210987687654321 876543210987654321 8765876543210987687654321 321 54321
21 21 31 1 365 21 65 21 21 21 2109876543211 210987654332 21 32143210987654321 21 2109876543321 221 1 32143210987654321 6543210987654321 21 2 32 1 32143210987654321 21 25 1 5 21 21 2109876543211 21 32543210987654321 2109876543321 2109876543321 1 21 1 32143210987654321 1 23 4 2 1 61 212109876543210987654326543210987654321 412109876543210987654321143210987654321 3 25 1 321 2 21 2098765454321 8765 121987654321 1 310 1198765454321 21 87654210 20 654321 1 21 87654321987654321 1198732654321 80 321321 54243210987654321 223210 311321987654321 1 441 1765487154321 8765487654321 54321210987654321 1765487654321 8 321 1 54321210987654321 243 1 21 2198765454321 10 321 87654321987654321 1 210 2198765454321 10 321 1 87654321987654321 1 210 21 20 10 321 541 87654321987654321 1 2 3 21 1198765454321 2198765432321 21 87654210987654321 110 221 21 2198765454321 10 321 21 87654321987654321 110

(ADDRESS)
654321 654321 654321 654321
65432121 321 523 65454321 341 654343 321 521 65454321 32121 21 5432121 321 543 5454321 5432121 321 543 5454321
CLK t CKS CKE >tCKS
tRCD t RAS tRC
SDRAM
Austin Semiconductor, Inc.
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures 22 and 23.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
AS4SD4M16
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9=0).
T0
CLK
T1
T2
T3
T4
T5
CLK
T0
T1
T2
T3
T4
T5
T6
CKE

CKE

INTERNAL CLOCK
INTERNAL CLOCK COMMAND

COMMAND
NOP

WRITE

NOP

NOP

READ

DQ

DOUT n

DOUT n+1

DOUT n+2

DQ
DIN n
DIN n+1
DIN
n+2
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW.
Figure 22 CLOCK SUSPEND DURING WRITE BURST
Figure 23 CLOCK SUSPEND DURING READ BURST
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22
321 321
NOTE: For this example, burst length = 4 or greater, and DQM is LOW.
DON'T CARE

ADDRESS
BANK, COL n
ADDRESS
BANK, COL n

43214321143322143211432114321143211 432 543 5 3215 4325 4325 332 32 43 432 32 32 21 43214321143211143211432114321144321 421 52125 4325 4215 4215 421 43214332 532 4 43 43214321143211143211432114321144321 421143321143211432114321143211 32 52125 4325 4325 4325 432 4325 4325 4325 4325 321 543211 432 543211 432 543211 432 543211 432

NOP

NOP

NOP

NOP

5432154321165652325654226553221 5432 4341 1432311 4431 2 32 32 31 5432154321165654321432111543211 5432 4321 5653226 5321 32 4321 1434311 4432 31 21 1 5432154321165654325654326554321 5421 6654326554321 543211 4321 321 4321 6543211543211 543211 4321 654326 5432 6654326554321 54321 54321 54321 5454221553221 32326 4431 32 321 3111 321 5432116543211 34326 4321 53221 5432 2111 5454321554321
NOP
554321 4321 543211 4432 5321 321 554321 554321 4321 321 321 543211 4321 5432 554321
DOUT n+3
SDRAM
Austin Semiconductor, Inc.
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank while an access command with AUTO PRECHARGE enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ASI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below.
AS4SD4M16
READ with AUTO PRECHARGE 1. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 2. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prir to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
T4
T0
T1
T2
T3
T5
T6
T7
CLK

COMMAND
BANK n
NOP

READ-AP BANK n

NOP

READ-AP BANK m

NOP

NOP

NOP
NOP
Internal States
BANK m
Page Active

READ with burst of 4

Interrupt Burst, Precharge
Idle

tRP - BANK n

tRP-BANK m Precharge

ADDRESS DQ
BANK n, COL a

BANK m, COL d

DOUT a

DOUT a+1

CAS Latency = 3 (BANK n)

NOTE: DQM is LOW.
CAS Latency = 3 (BANK m)
Figure 24 READ WITH AUTO PRECHARGE INTERRUPTED BY A READ
T0 T1

T2
T3
CLK

COMMAND
BANK n
READ-AP BANK n

NOP

NOP

NOP

WRITE-AP BANK m

NOP

NOP
Internal States
BANK m
Page Active

READ with burst of 4

Interrupt Burst, Precharge

tRP - BANK n

Page Active

DQM1 DQ

DOUT a

DIN d
DIN d+1
DIN d+2

DIN d+3

ADDRESS
BANK n, COL a
BANK m, COL d

CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
Figure 25 READ WITH AUTO PRECHARGE INTERRUPTED BY A WRITE
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
23
7654321 7654 6 32 543 6321 543 76543215432132165432121765432121 65432212165432121765432121 76313 7 6321 541 7 6321 543 6321 543 76543215432112165432121765432121 6 76323 7 6543 54 6543 76543215432112165432121765432121 6 76323 7 6543 54 6543
WRITE with burst of 4

tWR-BANKm Write back

432 4321 4321 1 4321
76543211 321 65432 76654321 321 654 54332 76543211 32121 654324 35 6 543 7351 321 654 65432132765432121654321321 32132165432121654321321 621 7 6321 51 1 6541 4 323 7624 65432132165432121654321321 654 1 6543 7654 65432132765432121654321321 654 7 6543 7654

7654321 7654 6 6543 354 6 76543215432112165432121765432121654321321 65432112165432121765432121654321321 74323 7 6543 6543 7 6543 6321 543 654 76543215432112165432121765432121654321321 6 74323 7 6321 654 543 4543 6 321 651 54 76543215432112165432121765432121654321321 6 74323 7 6321 432 654 543 4321 6543 624

765432121 6543 765432121 6543 4321 765432121 4323 6543 765432121 6541

Page Active

READ with burst of 4

654321321 4321 7654 657654321 321 654321321 4321 7654 321 657654321
DOUT d
DOUT d+1
T4
T5
T6
T7
NOP Idle
Don't Care
SDRAM
Austin Semiconductor, Inc.
WRITE with AUTO PRECHARGE
3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 4
AS4SD4M16
Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank 1 (Figure 27).
T0
T1
T2
T3
T4
T5
T6
T7
CLK

COMMAND
BANK n
NOP

WRITE-AP BANK n

NOP

WRITE-AP BANK m

NOP

NOP

NOP
NOP
BANK m
Page Active

READ with burst of 4

ADDRESS DQ
BANK n, COL a

BANK m, COL d

DIN a

CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 26 WRITE WITH AUTO PRECHARGE INTERRUPTED BY A READ
T0 T1

DIN a+1

T2
T3
T4
T5
T6
T7
CLK

COMMAND
BANK n
NOP

WRITE-AP BANK n

NOP

NOP

WRITE-AP BANK m

NOP

NOP

ADDRESS DQ
BANK n, COL a

BANK m, COL d

DIN a
NOTE: DQM is LOW.
Figure 27 WRITE WITH AUTO PRECHARGE INTERRUPTED BY A WRITE
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
24
31 321 321 321 2
DIN a+1
DIN a+2
DIN d

654321 6543 7 7654 7 7654 654 654 65432165432121654321321654321321 765432121654321321654321321 6321 543 7321 7 7321 65432165432121654321321654321321 7 6321 543 7321 7 7321 654 654 65432165432121654321321654321321 7 6543 7654 7 7654
7654543 6 4321 7621 321 654 765432121654321321 432121657621321 6321 543 4354 765432121657354321 4321 6543 765432121657654321 6543 4321
765654321 4323 6521 2 765432121 4321 341 765654321 31 765654321 4321
BANK m
Page Active

Internal States
Page Active

WRITE with burst of 4

Interrupt Burst, Write back tWR - BANK n

WRITE with burst of 4

7654321 632 6 54 543 4321 6543 321 4321 6543 76543215433212165432121765632321765432121 65432112165432121765454121765454121 6223 7 6321 513 7 6321 4 543 321 4321 6323 76543215433112165432121765432121765432121 6 6343 7 6543 5 543 4323 6321 541 6321 76543215432112165432121765654321765654321 6 6223 7 6321 54 4543 4321

Internal States
Page Active

WRITE with burst of 4

Interrupt Burst, Write back tWR - BANK n
Precharge

tRP-BANK n
tRP-BANK m

765654321 4521 3 321 765634321 4321 321 765654321 4321 21 765654321 4321
765432121 4321 4321 6543 765654321 4321 765432121 4321 6543 765654321 4321
DOUT d
DOUT d+1
NOP
Precharge tWR-BANK m Write back
tRP-BANK n
DIN d+1
DIN d+2
DIN d+3
Don't Care
SDRAM
Austin Semiconductor, Inc.
TRUTH TABLE 2-CKE1,2,3,4
CKEn-1 L CKEn L CURRENT STATE Power-Down Self Refresh Clock Suspend Power-Down Self Refresh Clock Suspend All Banks Idle All Banks Idle Reading or Writing COMMANDn ACTIONn X Maintain Power-Down X Maintain Self Refresh X Maintain Clock Suspend COMMAND INHIBIT or NOP Exit Power-Down COMMAND INHIBIT or NOP Exit Self Refresh X Exit Clock Suspend COMMAND INHIBIT or NOP Power-Down Entry AUTO REFRESH Self Refresh Entry VALID Clock Suspend Entry See Truth Table 3 NOTES
AS4SD4M16
L
H
5 6 7
H H
L H
NOTE: 1. 2. 3. 4. 5. 6.
7.
CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n . All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1.
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
25
SDRAM
Austin Semiconductor, Inc.
AS4SD4M16
TRUTH TABLE 3 - CURRENT STATE BANK n - COMMAND TO BANK n (Notes 1 to 6; notes appear below and on next page)
CURRENT STATE CS\ RAS\ CAS\ WE\ COMMAND (ACTION) ANY H L L L L L L L L L L L L L L L L X H L L L L H H L H H L H H H L H X H H L L H L L H L L H H L L H H X H H H L L H L L H L L L H L L L COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE NOTES
Idle
Row Active
7 7 11 10 10 8 10 10 8 9 10 10 8 9
Read ( AutoPrecharge Disabled)
Write ( AutoPrecharge Disabled)
NOTE:
1. 2. 3. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/AutoPrecharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4.
AS4SD4M16 Rev. 1.5 10/01
26
SDRAM
Austin Semiconductor, Inc.
NOTE (continued):
The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. 5.
AS4SD4M16
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
27
SDRAM
Austin Semiconductor, Inc.
AS4SD4M16
TRUTH TABLE 4 - CURRENT STATE BANK n - COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page)
CURRENT STATE Any Idle Row Activating, Active or Precharging Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (with AutoPrecharge) Write (with AutoPrecharge) CS\ H L X L L L L L L L L L L L L L L L L L L L L RAS\ X H X L H H L L H H L L H H L L H H L L H H L CAS\ X H X H L L H H L L H H L L H H L L H H L L H WE\ X H X H H L L H H L L H H L L H H L L H H L L COMMAND/ACTION COMMAND INHIBIT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any command otherwise allowed to bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE NOTES
7 7
7, 10 7, 11 9 7, 1 7, 13 9 7, 8 ,14 7, 8 15 9 7, 8 16 7, 8 17 9
NOTE:
1. 2. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/ accesses and no register accesses are in progress. Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated. Read w/AutoPrecharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. All states and sequences not shown are illegal or reserved. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3.
4. 5. 6. 7.
AS4SD4M16 Rev. 1.5 10/01
28
SDRAM
Austin Semiconductor, Inc.
NOTE (continued):
8. 9. 10. 11. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted by bank m's burst. Burst in bank n continues as initiated. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7). For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).
AS4SD4M16
12.
13.
14.
15.
16.
17.
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
29
SDRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD/VDDQ Supply Relative to VSS ........................................ -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ........................................ -1V to +4.6V Operating Temperature, TA (ambient)........-55C to +125C Storage Temperature (plastic) ................-55C to +150C Power Dissipation ................................................. 1W
AS4SD4M16
*Stresses greater than those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 6) (-55 +125 C ; VDD/VDDQ =+3.3 V +0.3V)
PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs INPUT LEAKAGE CURRENT Any input 0VSYMBOL VDD/VDDQ VIH VIL II IOZ VOH VOL
MIN 3 2.2 -0.5 -5 -5 2.4 --
MAX 3.6 VDD +0.3 0.7 5 5 -0.4
UNITS V V V V V
NOTES 23 23
IDD SPECIFICATIONS AND CONDITIONS1, 6, 11, 13 (-55C

+3 , <:=5 &65 1@/

)85(<* ( ( .&/ %
0 &/ ;
012 ! 3&45/%0&4( &65 )) 78(9 :6)5 "+; ( ( .&/ %
012 <:=5 &65 ", -,

)) 78(9 8<:=5 8.5/ 5 & 8<<55 :( >/&?/5
, ! 1@/ &65 &(:(@&@ 7@/
( ( .&/ %

+3
)) 78(9 8<:=5 )85(<* +
", -,
0 &/ ;
( ( .&/ %

( ( .&/ %

! "#$ % & ' &()*
AS4SD4M16 Rev. 1.5 10/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
30
SDRAM
Austin Semiconductor, Inc.
CAPACITANCE
PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs SYMBOL CI1 CI2 CIO MAX 4.0 5.0 6.5 UNITS pF pF pF NOTES 2 2 2
AS4SD4M16
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 5, 6, 8, 9, 11) (-55oCPARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time ACTIVE to PRECHARGE command AUTO REFRESH, ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4,096 rows) -40 to +85 degrees C Refresh period (4,096 rows) -55 to +125 degrees C PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command
AS4SD4M16 Rev. 1.5 10/01
SYM CL = 3 CL = 2 tAC tAC tAH tAS tCH tCL CL = 3 CL = 2 tCK tCK tCKH tCKS tCMH tCMS tDH tDS CL = 3 CL = 2 tHZ tHZ tLZ tOH tRAS tRC tRCD tREF tREF tRP tRRD tT A2 version tWR tXSR
-8 MIN MAX 6.5 9 1 2 3 3 8 12 1 2 1 2 1 2 6 7 1 2.5 50 80 20 64 16 24 20 0.3 1 CLK + 8ns 15 80 1.2 30 20 80,000 1 2.5 60 90 30 1 3 3.5 3.5 10 15 1 3 1 3 1 3 MIN
-10 MAX 7 9
UNITS NOTES ns ns ns ns ns ns ns ns ns ns ns ns ns ns 24 22, 24 22
8 10
ns ns ns ns
10 10
80,000
ns ns ns 22 22
64 16
ms ms ns ns 22
1 1 CLK + 8ns 15 90
1.2 -
ns
7 25 26 20
ns ns
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
31
SDRAM
Austin Semiconductor, Inc.
AC FUNCTIONAL CHARACTERISTICS5, 6, 7, 8, 9, 11 (-55oCPARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command A1 version Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command A2 version A2 version A2 version SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH -8 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 -10 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 UNITS NOTES tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 27 17 17
AS4SD4M16
LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2
ELECTRICAL TIMING CHARACTERISTICS for -8 SPEED5, 6, 7, 8, 9, 11, 24 (-55oC-8 PARAMETER Access times from CLK (pos. edge) CL = 3 CL = 2 Clock cycle time ACTIVE to READ or WRITE delay PRECHARGE command period AUTO REFRESH, ACTIVE command period WRITE recovery time 100 MHz Speed Reference (CL -tRCD-tRP) A2 Version CL = 3 CL = 2 SYM tAC tAC tCK tCK tRCD tRP tRCD tWR MIN ----8 12 20 24 80 2 3-2-3 MAX 6 9 ------------UNITS ns ns ns ns ns ns tCK --CLKs NOTES 22 22 22 22 22 22 21 -----
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
32
SDRAM
Austin Semiconductor, Inc.
NOTES
All voltages referenced to VSS. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25C; pin under test biased at 1.4V. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55C TA +125C) is ensured. 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. 1. 2. 12. Other input signals are allowed to transition no more than once in any 30ns period (20ns on -8) and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 19. Address transitions average one transition every 30ns (20ns on -8). 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 100 MHz for -8 and 66 MHz for -10. 22. These five parameters vary between speed grades and define the differences between the -8 SDRAM speeds: -8. 23. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 24. The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 25. Auto precharge mode only. The precharge timing budget ( tRP) begins 8ns after the first clock delay, after the last WRITE is executed. 26. Precharge mode only. 27. JEDEC and PC100 specify three clocks.
AS4SD4M16
Q 50pF
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
33
4321 4321 4321 4321
4321 4321 4321
Precharge all banks AUTO REFRESH AUTO REFRESH Program Mode Register 1,3,4
452321 341 2 432321 321 541 454321 1 454321 343 521 21 21 432121
54321 54321 6 4321 21 54354321098765432121098765432109876543210987654321 1 654 4321 543213210987654321210987654321098765432109876554321 154 6213210987654321210987654321098765432109876554321 541213210987654321210987654321098765432109876554321 1 654 354 4321 21 21 543213210987654321210987654321098765432109876554321 6 4321
CODE
4321 10 4310987654321 21 10 2198765432 4321987654321 4310987654321 21 10 21 1 4321987654321 21
54321 454321 321 2 454321 321 1 454321 321 4321
54321121 1321 4543 544323 1 354 54421121 1543 4211 332121 54132121 1323 3211 54 54321121 4543 543543 154 4 54321121 121321 4321 54121121 1323 3321 54 4323 54321121 454
5432109876543210987654321098765454321 211 12 321 21 5410987654321 21 109 321 541 09876543210987654321098765432 2 3 54 5432187654321 21 32 5412109876543210987654321098765432321 21 121 311 2 323 54121 21 1 5410987654321 211 109 2 5421109876543210987654321098765432121 21 321 543 21 1 5410987654321 21 32 5432109876543210987654321098765454321 1 5432187654321 211 5431 20 1 5432187654321098765432121098765432109876543210987654321 221 119876543210987654321210987654321098765432109876543 1 0 5421187654321098765432121098765432109876543210987654321 209 329 119 5432187654321098765432121098765432109876543210987654321 10 2
SINGLE BANK ALL BANKS
098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543212109876543210987654321098765432121098765432109876543210987654321 098765432109876543212109876543210987654321098765432121098765432109876543210987654321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321
NOP
PRECHARGE AUTO REFRESH NOP NOP AUTO REFRESH NOP NOP LOAD MODE REGISTER NOP ACTIVE
54321 1 3 54321 1 321 31 54321 121 54321 12
21 21 21 21 41 243221 41 12 21 21 213221 12 243211 213211
32 211 321 21 4 313 3 2232121 2 43 343 321 2112121 3212121 2112121 43
321 21 321 21 42 3213211 41 12 324 21 3213211 3213211 3213221 42
21 321 21 321 43 2132121 41 13 24 321 2132121 2132121 2132321 43
321 21 321 21 42 3213211 42 12 324 21 3213211 3213211 3213211 42
21 32 21 211 43 213212 42 1 22 24 12 2132111 3 2132211 2132111 43
321 21 321 21 41 1 3213211 42 12 324 21 3213221 3213211 3213221 4
21 21 21 21 41 243221 41 11 21 21 213221 11 243221 213221
32 121 211 321 4 323 3 2432121 2 4 13 311 321 2212121 3412321 2132121
t CK
3213 1 1 5 321321 1 5 24 354321 14 51 321321 14 2
A0-A9, A11
COMMAND
DQM / DQML, DQMH
CKE
CLK
t CMH t CMS t CMH t CMS t CMH tCMS
tCKS tCKH
Austin Semiconductor, Inc.
T0
INITIALIZE AND LOAD MODE REGISTER2
T1
Tn+1
tCH
To+1 tCL
tAS
tAS
Tp+1
CODE
tAH
tAH
4543 321 21 454321 32121 432321 321 541 2 454321 21 1 454321 321
NOTE:
AS4SD4M16 Rev. 1.5 10/01
* CAS latency indicated in parentheses.
TIMING PARAMETERS
SYMBOL*
BA0, BA1
tAH
tCL
tCH
tAS
tCK (2)
tCK (3)
tCKH
1. 2. 3. 4.
A10
DQ
The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a "Don't Care". JEDEC and PC100 specify three clocks. Outputs are guaranteed High-Z after command is issued.
MIN
T=100s
12
Power-up: VDD and CLK stable
1
8
3
3
2
1
-8
High-Z
MAX
ALL BANKS
MIN
3.5
3.5
10
15
1
3
1
tRP
-10
MAX
tRC
UNITS
ns
ns
ns
ns
ns
ns
ns
34
SYMBOL* tMRD (3) tCMS tCMH tRP tCKS tRC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
tRC
MIN
24 80 2 2 1 2 -8 MAX
MIN
30 90
tMRD
2
3
1
3
AS4SD4M16
Tp+2
-10
SDRAM
MAX
BANK
ROW
ROW
Tp+3
UNITS
Undefined
Don't Care
tCK
ns ns ns ns ns
321 321
654 321 324321 651321 1 324321 651 1 321 654321
5431 26 5432143212109876543210987654321098765432121098765432109876543210987654321 22143212109876543210987654321098765432121098765432109876543210987654321 15 65 5432143212109876543210987654321098765432121098765432109876543210987654321 265 1 5432143212109876543210987654321098765432121098765432109876543210987654321 215 6
1098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543212109876543210987654321098765432121098765432109876543210987654321 321 321 54211 32 654321 321 321 54321 76 321 321 5471143210987654321098765432121 225432109876543210987654321 365 6523 4 321 321 54321 321 321 5421143210987654321098765432121 22 5 72 5 36 6 6541 43 3 321 321 54321 321 321 5471143210987654321098765432121 36 6521 321 321 54321 321 321 5421143210987654321098765432121 325 7 6543 321 321 54321
tCKS tCMS tCKH tCMH NOP NOP NOP ACTIVE
T0
Austin Semiconductor, Inc.
T1
T2
3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321
CLK
tCK
t CL
t
CK
POWER-DOWN MODE1
t CH
t
CK
21 321 21 321 41 2132321 41 13 21 321 2132321 43 2432121 2132121
21 21 21 21 41 213221 41 12 21 21 213221 42 243211 213211
54321 54321 54321 54321
21 321 21 321 41 2132121 41 13 21 321 2132321 43 2132121 2432321
32121 21 3 32121 21 3 1 32321 21 3 32121
A0-A9, A11
COMMAND PRECHARGE
DQM / DQML, DQMH
CKE
ALL BANKS
654 321 1 324321 651321 324321 654 1 1 321 651321
654354 21 6 4321 21 654321321098765432109876543212109876543210987654321098765654321 2621321098765432109876543212109876543210987654321098765652121 154 4343 652121321098765432109876543212109876543210987654321098765432121 2654 4354 1 6521 4343 21 21 654321321098765432109876543212109876543210987654321098765654321 6
54321 54321 54321 54321
A10
tAS tAH
654 321 1 324321 651321 324321 654 1 321 651321
654354 21 6 4321 21 654321321098765432109876543212109876543210987654321098765654321 2621321098765432109876543212109876543210987654321098765652121 154 4343 652121321098765432109876543212109876543210987654321098765432121 2654 4354 1 6521 4343 21 654321321098765432109876543212109876543210987654321098765654321 6
54321 54321 54321 54321
BA0, BA1
Precharge all active banks
DQ
High-Z
SINGLE BANK
BANK(S)
Two clock cycles
All banks idle, enter power-down mode
Input bufferd gated off while in power-down mode
Exit power-down mode
4321 2 4321 4321 4321 31
NOTE:
AS4SD4M16 Rev. 1.5 10/01
* CAS latency indicated in parentheses.
TIMING PARAMETERS
SYMBOL*
tAH
tCK (3)
tCL
tCH
tAS
1. Violating refresh requirements during power-down may result in a loss of data.
MIN
8
3
3
2
1
-8
MAX
MIN
3.5
3.5
10
3
1
-10
MAX
UNITS
ns
ns
ns
ns
ns
35
SYMBOL* tCK (2) tCMS tCMH tCKS tCKH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MIN
12
2 1 2 1 -8 MAX
Tn +1
MIN
All banks idle
15
3 1 3 1 -10 MAX
AS4SD4M16
SDRAM
Tn +2
BANK
ROW
ROW
UNITS
ns
ns ns ns ns
Undefined Don't Care
4321 4321 4321 541656543 3 3 7 54721432121 121432121 3656541 54721432121 1656523 365 4 54121432121 3 6543 7 545 3 25 5412121 232121 4141 341 343 5412121 2323 5 5212121 4343 5
762132121 54543 76 43 762132121 21213 43313 5454 76 764322121 5454 76 764321121 21323 5451 76 762122121 4334 54213 7654 7657654321 14321 7657654321 14321 7657654321 14321 7657654321 14321 7657654321 14321
4321 4321 4321 4321
21 1 41 213221 43221 24 21 213221 11 213221 41 54321 54321 54321 54321
21 3 1 2 232109876543221 12109876543211 21 232109876543211 1 2 2 212109876543211 3 21 54165 651 3 7 4 7214321321 541214321321 165 651 365 654 4 547214321321 3 541214321321 365 654 7
321 5 2 1 32543212109876543210987654321098765432321 143212109876543210987654321098765432321 21 11 321 32543212109876543210987654321098765432321 1 2 1 32143212109876543210987654321098765432321 5 21 11 321 321 321 321 321 321 321 321 321 321 321 321
NOP NOP NOP
3213211 4 12 3243211 42 321 21 3243211 12 2 3213211 321 321 321 321
NOP
523217654321 2121 4098 1 0 398 540987654321 520987654321 23 4121 1 543217654321 321 321 321 321
READ
65214354321 4321221 543 1 65212154321 4521221 31 65254352121 4143243 31 65212154321 43 221 51
54321 54321 54321 54321
21 1 21 21 4 43221 21 21 243221 11 1 21 21 213221 213221 41
311 321 2432121 2 4 321 3 2432321 2 1 311 321 223 121 3412121 2132121
654321 654321 654321 654321
54321 54321 54321 54321
321 2 321 21 4 43211 321 21 3243221 12 321 11 3213211 3213211 42 2
21 3 21 321 4 432121 21 321 2432321 13 21 121 2132121 2132121 43 3
313 321 2412121 2 4 321 3 2432321 2 1 311 321 223 121 3412121 2132121
654321 654321 654321 654321
54321 54321 54321 54321
tCL
21 11 243221 1 42 24 11 213221 11 12 2 21 21 243211 213221
t CK
21 21 243221 1 41 24 21 213221 11 12 1 21 21 243211 213221
COMMAND
DQM / DQML, DQMH
CKE
CLK
tCKS t CKH tCMS tCMH
tAS t AH
1 8 543 3 17654321098765432121 87654321098765432121 541 87654321098765432121 1 543 3 17654321098765432121 8 541 1098765432109876543221 1 1098765432109876543221 2 11 1098765432109876543221 1 1098765432109876543211 2 2 1098765432109876543211 21 21 1 54121 3 8 1 876543210987654321 543 17654321098765432121 87654321098765432121 543 1 87654321098765432121 541 3 17654321098765432121 8 541 3
52154 43 6 321 541 5262132109876543212109876543210987654321098765432321 412132109876543212109876543210987654321098765454121 354 323 5262132109876543212109876543210987654321098765432121 4354 3 541 1 3 5212132109876543212109876543210987654321098765454321 4154 6 321987654321098765432121098765432109876543210987654321 0 321 3209876543210987654321210987654321098765432109876543211 1 2 2 3209876543210987654321210987654321098765432109876543211 1 21 321 320 1 2 2 11 3219876543210987654321210987654321098765432109876543221 3219876543210987654321210987654321098765432109876543211 0 21 52121 43 54321 1 6 321 1 52654321098765432121098765432109876543210987654541 4154 3 323 5262132109876543212109876543210987654321098765454321 412132109876543212109876543210987654321098765432121 354 5262132109876543212109876543210987654321098765432121 4354 3 321 543 1 5212132109876543212109876543210987654321098765454321 4154 6
54321 54321 54321 54321 21 22 221 1 1 211 21 21 1 2 221 211 54321 54321 54321 54321 54321
A0-A9, A11
BA0, BA1
A10
tAS t AH
tAS t AH
COLUMN m2
BANK
T0
Austin Semiconductor, Inc.
tCMS tCMH
T1
tCH tCKS tCKH
T2
NOP
tAC
CLOCK SUSPEND MODE1
T3
T4
tAC tOH
T5
tHZ
T6
tDS tDH
54321 54321 54321 54321
NOTE:
AS4SD4M16 Rev. 1.5 10/01
* CAS latency indicated in parentheses.
TIMING PARAMETERS
SYMBOL*
tAC(3)
tAC(2)
tCKH
tAH
tCK(2)
tCK(3)
tCL
tCH
tAS
DQ
1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled. 2. x16: A8, A9 and A11 = "Don't Care."
MIN
12
1
8
3
3
2
1
-8
MAX
6.5
9
MIN
3.5
3.5
10
15
1
3
1
tLZ
-10
MAX
7
9
UNITS
DOUT m
ns
ns
ns
ns
ns
ns
ns
ns
ns
36
SYMBOL* tCKS tLZ tHZ(2) tOH tHZ(3) tDS tDH tCMS tCMH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
DOUTm+1
MIN
2.5 1 2 1 2 1 2 -8 MAX 7 6
COLUMN e2
WRITE
BANK
DOUT a
T7
MIN
2.5 1 3 1 3 1 3 -10 MAX 10 8
T8
AS4SD4M16
SDRAM
UNITS
ns
ns
ns ns ns ns ns ns
DOUT a-1
ns
Undefined Don't Care NOP T9
543 1 54321 54321 54221 2 3 31
321 321
4652121 3211 6543 2 4324321 1 4321121 6521 2 4 4321321 6543
5421109876543210987654321098765432121098765432109876543210987654321 32 2 5422109876543210987654321098765432121098765432109876543210987654321 311 5422109876543210987654321098765432121098765432109876543210987654321 32 2 5421109876543210987654321098765432121098765432109876543210987654321 311
765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 765432109876543212109876543210987654321098765432121098765432109876543210987654321 321 321 21 321 321 321 321 54321 321 321 21 21 321 321 321 321 54321 321 321 21 21 321 321 321 321 54321 321 321 21 21 321 321 321 321 54321 321 321 21 21 321 321 321 321 54321
tCKS tCMS
PRECHARGE
2113321 324 221 1 2143221 321 32 1 2 2113311 324 221 2143211 321 321
21 321 21 321 43 2132121 43 13 24 321 2132121 2132121 2132121 43
321 21 21 21 42 3213211 21 21 42 11 3213211 243211 3213221 42
321 21 321 21 41 3243221 41 12 321 21 3213221 12 3243211 3213211
21 321 21 321 43 2132121 43 13 24 321 2132121 2132121 2132121 43
t CH
321 21 321 21 41 3243221 41 11 321 21 3213221 11 3243221 3213221
32 121 211 321 4 323 3 2432121 2 4 13 311 321 2212121 3412321 2132121
21 21 3 2321 3 1 21 2121 1 2321 2121
COMMAND
A0-A9, A11
DQM / DQML, DQMH
CKE
CLK
ALL BANKS
4654 324 1 4321321 651321 4321321 651 4 4321321 651 4
652198 43 0 6541 2 652021765432109876543212109876543210987654321098765432121 4121765432109876543212109876543210987654321098765654321 398 4323 652021765432109876543212109876543210987654321098765432121 4398 3 4341 6521 21 23 1 652121765432109876543212109876543210987654321098765654321 4198 0
54321 54321 54321 54321
A10
tAS tAH
54651321 324 654 1 54321321 54321321 654 4 54321321 651
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
652198 43 0 6541 2 652021765432109876543212109876543210987654321098765432121 4121765432109876543212109876543210987654321098765654321 398 4323 652021765432109876543212109876543210987654321098765432121 4398 3 4341 6521 23 1 652121765432109876543212109876543210987654321098765654321 4198 0
54321 54321 54321 54321
AS4SD4M16 Rev. 1.5 10/01
* CAS latency indicated in parentheses.
BA0, BA1
TIMING PARAMETERS
SYMBOL*
tAH
tCK (2)
tCK (3)
tCL
tCH
tAS
DQ
High-Z
MIN
SINGLE BANK
12
8
3
3
2
1
BANK(S)
Austin Semiconductor, Inc.
T0
tCKH tCMH
-8
MAX
tCK
NOP
T1
MIN
t RP
3.5
3.5
10
15
3
1
-10
MAX
AUTO REFRESH MODE1
AUTO REFRESH
T2
UNITS
ns
ns
ns
ns
ns
ns
NOP
37 t RC
SYMBOL* tRP tCKH tRC tCMS tCMH tCKS
NOP
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
t CL
AUTO REFRESH
Tn +1
MIN
24 80 2 1 2 1 -8 MAX
NOP
t RC
MIN
30 90
NOP
3
1
3
1
AS4SD4M16
-10
To +1
MAX
SDRAM
BANK
ROW
ROW
ACTIVE
UNITS
ns
ns
ns
ns
ns ns
Undefined Don't Care
09876543212109876543210987654321098765432121098765432109876543210987654521 31 54321 0987654321210987654321098765432109876543212109876543210987654321098765454321 34121 23 1 54321 0987654321210987654321098765432109876543212109876543210987654321098765454321 321 54321 0987654321210987654321098765432109876543212109876543210987654321098765454321 321 1 54321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432109876543212109876543210987654321098765432121098765432109876543210987654321 321 321 6521211098765432121 43 543 321 321 54321 54 4 321 321 6521211098765432121 2332 4432 543 3 321 321 54321 321 321 6551211098765432121 4332 541 321 321 54321 321 321 6551211098765432121 2332 44 5 541 3 321 321 54321
tCKS tCKH tCMS tCMH
ALL BANKS
T tCK
Austin Semiconductor, Inc.
T
SELF REFRESH MODE1
T
3210987654321 3210987654321 3210987654321 3210987654321 1 3210987654321 3210987654321 321098765432
CLK
t
CH
t CL
t
CKS
t
RAS
321 2 42 321 21 3213211 42 4 11 3213211 3243221 12 321 11 3213211 3213221 42
21 2 42 21 21 213211 4 4 11 213221 243221 12 21 11 213211 213211 42 2
654321 654321 654321 654321 654321
321 21 11 42 321 11 3243221 42 3243211 3213221 11 12 321 21 3243211 3213221
21 1 3 21 1 2321 3 232 212 1 1 21 1 2321 2121
A0-A9, A11
COMMAND PRECHARGE
DQM / DQML, DQMH
CKE
A10
tAS tAH
0987654321210987654321098765432109876543212109876543210987654321098765454321 321 0987654321210987654321098765432109876543212109876543210987654321098765454321 321 0987654321210987654321098765432109876543212109876543210987654321098765454321 321 1 0987654321210987654321098765432109876543212109876543210987654321098765454321 321 0987654321210987654321098765432109876543212109876543210987654321098765454321 321
54321 54321 54321 54321 54321
BA0, BA1
DQ
Precharge all active banks
High-Z
SINGLE BANK
BANK(S)
tRP
NOP
Enter self refresh mode
AUTO REFRESH
T
Exit self refresh mode (Restart refresh time base)
432 4321 1 4321 4321
CLK stable prior to exiting self refresh mode
4321 4321 4321
AS4SD4M16 Rev. 1.5 10/01
NOTE: 1. Self Refresh Mode available on Industrial Temperature Range option only.
TIMING PARAMETERS
* CAS latency indicated in parentheseses.
SYMBOL*
tAH
tCKH
tCK(2)
tCK(3)
tCL
tCH
tAS
MIN
12
1
8
3
3
2
1
-8
MAX
MIN
10
15
1
4
4
3
1
-10
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
38
SYMBOL* tCKS tXSR tRP tRAS tCMS tCMH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MIN
80 24 50 2 1 2
NOP
-8
80,000
MAX
tXSR
t CKS
MIN
60
90 30 3 1 3
T
AS4SD4M16
-10
SDRAM
80,000
MAX
AUTO REFRESH
UNITS
Undefined
Don't Care
ns
ns
ns
ns
ns ns
T
54321 54321 54321 54321
21 21 21 21 21 21 21 21 21
5432121 6543 5432121 6543 5432121 6543 5432121 6543 5432121 6543 5432121 6543 5432121 6543 5432121 6543 5432121 6543 5432121 6543 6543 5432121 5432121 6543 5432121 6543 5432121 6543 5432121 6543
65432121 76543 65432121 54323 76541 65432121 76543 65432121 76543 65432121 54321 76543 65432121 56541 74323 432 654323 76543 65432121 5432121 76541 65432121 56541 73 65432121 76543
765432143210987654321321 765 7654 765476543210987654321321 3 7654 765472143210987654321321 321 65 7654 765432143210987654321321 365 7654 765472143210987654321321 765 7654 765432143210987654354321 98765 21 769876543210987654324 59876 0 32 51 760432154321098765432321 08765543210987654343 9432143210987654322121 59876543210987654511 9876 8765 769432143210987654321121 58765543210987654543 54 765432143210987654321321 99876 0 321
657654654321 765432 4321321 657654654321 4321321 654321654321 1 654321321321 7654321 4321654 657654654321 328767654321 1 54321 4381 54321 3227676543 2 1 4311 5432121 328767654321 1 4381 54321 3227676543 2 1 1 4311 5432121 328767654321
4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321
654321 7654321 2 65421098765432109876543210987654321 310 7654 65422198765432109876543210987654321321 32198765432109876543210987654321321 10 7654 65432198765432109876543210987654321321 310 7654 65422198765432109876543210987654321321 210 7654 323 3 2112121 4 34 2132 2 341 321 2112121 23 321 343 3 213 121 23 3212121 2112121 4 321 321 321 321 321 323 3 2112121 4 34 2132 2 341 321 2112121 23 321 343 3 213 121 23 3212121 2112121 4 21 21 21 21 21
7684321654321 5 7687654654321 54321321 7654321 7684321654321 57654321 7684321321321 57654321 7687654654321 54321654
7654321 7654321 7654321 7654321 7654321
21 21 21 21 21
21 21 21 21 21
321 321 321 321 321
21 21 21 21 21
21 21 21 21 21
321 321 321 321 321
4321 4321 4321 4321 4321
3213321 52 3213221 214 211 54 31 321 321 25 32 5 1 1 2 3213211 214 311 3213221 2143221 54
21 21 12 4 3213211 243221 3213211 21 21 42 12 3213211 24 11 3213211 42 2
21 21 12 4 3213211 243221 321 11 21 21 42 11 2 3213211 243211 3213221 42
323 321 2 41 3 2132121 3412321 241 121 341 3 23 3 2132121 313 321 21 2112321 3232121 4
324 32 5 3513221 2113211 24 321 314 32 224 311 2 5 2 354 321 2113211 2 3213211 2113211 52
324 211 24 32 5 3513321 2113221 1 31 32 224 311 2 5 1 2 354 321 2113221 3213211 2113221 54
21 21 12 4 3213211 243221 321 11 21 21 42 11 2 3213211 243211 3213221 42
t CH
341 121 23 2132321 3432321 21 1 2132321 341 3 21 2412121 313 121 23 2132321 341 321 2
323 121 2 41 3 3412321 2132321 31 1 221 321 21 41 343 321 2112321 3232321 2112321 43 1
t CKH t CK
654321 654321 654321 654321 654321
t CKS
COMMAND
CLK
CKE
t CMS t CMH
Austin Semiconductor, Inc.
ACTIVE
T0
T1
NOP
READ -- WITHOUT AUTO PRECHARGE1
t CMS
t
CL
READ
T2
t CMH
19876543210987654321098765432121 0 43 09876543210987654321098765432121 1 43 3 1 09876543210987654321098765432121 4321 1 09876543210987654321098765432121 43 3 19876543210987654321098765432121 0 4321
NOP
PRECHARGE
3213211 4 32 324 32 3213221 1 3213211 4 321 321 311 4 32 1 3213211 3213221 42
987654321098765454321 543 321 5432 987654321098765454321 321 1 987654321098765432121 987654321098765454321 543 321 987654321098765432121 54321
DQM / DQML, DQMH
BA0, BA1
A0-A9, A11
A10
t AS
t AS
t AS
BANK
ROW
ROW
t AH
t AH
t AH
DISABLE AUTO PRECHARGE
COLUMN m2
BANK
T3
NOP
t AC
T4
NOP
tAC
t OH
T5
tAC
t OH
SINGLE BANK
ALL BANKS
BANK
T6
tAC
t OH
321 321 321 321 321 321 321
321 321 321 321 321 321 321
4321 4321 4321 4321 4321 4321 4321
87654321 87654321 87654321 87654321 87654321 87654321 87654321
DQ
t RAS
t RCD
t RC
5 3 21 44321 4321 4321
NOTE:
AS4SD4M16 Rev. 1.5 10/01
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A8, A9 and A11 = "Don't Care." * CAS latency indicated in parentheseses.
TIMING PARAMETERS
SYMBOL*
tAC(2)
tAH
tCKH
tAC(3)
tCK(2)
tCK(3)
tCL
tCH
tAS
tCKS
MIN
12
2
1
8
3
3
2
1
-8
MAX
6.5
9
MIN
3.5
3.5
10
15
3
1
3
1
-10
MAX
9
7
CAS Latency
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t LZ
39
SYMBOL* tRAS tLZ tHZ(2) tRCD tRC tCMH tOH tHZ(3) tCMS tRP
DOUT m
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MIN
2.5
24 20 80 50 1 2 1 -8 80,000
DOUT m+1
MAX
7
6
MIN
2.5
60
30 30 90 1 3 1
DOUT m+2
-10
80,000
MAX
10
8
t RP
AS4SD4M16
UNITS
T7
NOP
ns
ns
ns
ns
ns
ns
ns ns ns ns
DOUT m+3
SDRAM
tHZ
t OH
ROW
BANK
ROW
ACTIVE
T8
Undefined Don't Care
54321 54321 54321 54221 3 31 321 321 321
21 21 21 21 21 21 21 21
4321 4321 4321 4321 4321 4321
321 321 321 321 321 321
4321 4321 4321 4321 4321 4321
87654321 87654321 87654321 87654321 87654321 87654321
t AC
5432121 76543 5432121 76543 5432121 76543 5432121 76543 5432121 76543
65432109876543210987654321098767654321 21 54321 65212109876543210987654321098765432321 4 76541 65232109876543210987654321098765432321 4321 1 76541 65432109876543210987654321098767654121 4121 76541 65232109876543210987654321098765432321 21 54323
654321654321 658321432321 8765432 43216541 654765654321 1 654765432121 83214321 43216543 658765654321
321 321 321 321 321
5432121 6543 5432121 6543 5432121 6543 5432121 6543 5432121 6543
652121212109876543210987654321098765432121 4343 65 6521 43 656343212109876543210987654321098765432121 25 4 6543 43 656121212109876543210987654321098765432121 2121 4343 5 6521 656121212109876543210987654321098765432121 2343 45 6543 43 652121212109876543210987654321098765432121 4343 65 6521
65437654331 1 8 21 2 821654221 654376654311 1 3 54331 654876543221 12165421 82154322 654376543211 1 321 21 1 654876654321 12165432
321 321 321 321 321
654321 654321 654321 654321 654321
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
21 21 21 21 21
21 21 21 21 21
321 321 321 321 321
313 121 243 3 1 4 3212121 2212321 3212321 213 121 4 1 4 3212121 243 321 3212121 213 3
324 32 211 321 3213221 2143211 32 31 211 311 2 2 3243221 2143221 321 311 2113211 42
3243221 21 21 12 4 3213211 3243211 21 21 21 11 12 41 2 2 3213211 3213221 4
2412321 321 2 4 2132121 313 321 2412121 341 121 2 2132321 313 321 23 2112121 323 1 4
324 2 211 21 3213221 2143211 32 1 211 11 2 2 3243221 2143221 321 11 2113211 42
321 21 3243221 12 4 3213211 321 11 321 11 12 41 2 2 3243221 3213211 3213221 4
2412321 321 3 2 4 2132121 313 321 2412121 341 121 23 3 2132121 313 121 23 2112321 323 3 4
t CH
211 31 35 22 2143221 3543311 21 221 2543321 351 311 2 2143221 311 221 22 1 2143321 351 21 2
CL
3243221 21 21 12 41 3213211 3213221 21 21 24 11 11 42 12 3243211 3213221
t CK
654321 654321 654321 654321 654321
COMMAND
CKE
CLK
t CKS
t CMS t CMH
ACTIVE
Austin Semiconductor, Inc.
T0
t CKH
NOP
T1
t CMS
54323 7654 65432198765432109876543210987654321321 210 654 5432121 76543 65421098765432109876543210987654321321 3 654 5432121 7654121 3 65422198765432109876543210987654321321 321 10 654 5432121 210 76543 65432198765432109876543210987654321321 654 7654321 654321 654321 19876543210987654321098765432121 2143221 321 3 0 3 3 32 32 5 1 4 13 42 09876543210987654321098765432121 2113211 32132111 2432121 43222 213221 1 3 354 2 2 3 1 09876543210987654321098765432121 2513211 32432111 2432121 321 311 311 321 211 21 311 2 54 32 4 22 4 22 32 1 31 09876543210987654321098765432121 2113211 32132111 2132121 1 3 3 324 32 2 3 2 1 3 19876543210987654321098765432121 2113211 32132111 2132321 0 321 324 321 321 22 21 11 52 4 12 3 4 21
t CMH
654321654321 87654321 321 6587654323 43216541 321 654765654321 8321432121 321 658765432121 43216543 321 654321654321 321 9876543210987654541 2 6 7 53 8323 2 1 65644321 87 51 98765432109876543624321 87 53 2 1 98765432109876565644321 6543 2 1 43624321 87 51 87 51 98765432109876565644321 43624321 87 53 1 98765432109876543624321 87 51 2 1
t AS
NOTE:
AS4SD4M16 Rev. 1.5 10/01
SYMBOL* tAH tAC(2) tCKH tCK(2) tCK(3) tCL tCH tAS tAC(3) tCKS
DQM / DQML, DQMH
MIN
12
2
1
8
3
3
2
1
-8
MAX
6.5
9
MIN
3.5
3.5
15
10
3
1
3
1
-10
MAX
7
9
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. For this example, the burst length = 4, the CAS latency = 2. 2. x16: A8, A9 and A11 = "Don't Care."
BA0, BA1
A0-A9, A11
A10
DQ
* CAS latency indicated in parentheseses.
TIMING PARAMETERS
SYMBOL*
t AS
tAH
tAC(2)
tCKH
tAC(3)
tCK(2)
tCK(3)
tCL
tCH
tAS
t AS
tCKS
BANK
ROW
ROW
t AH
t AH
t AH
t RAS
t RCD
t RC
MIN
12
2
1
8
3
3
2
1
-8
MAX
6.5
ENABLE AUTO PRECHARGE
9
MIN
READ -- WITH AUTO PRECHARGE1
3.5
3.5
t
10
15
3
1
3
1
READ
T2
-10
COLUMN m2
BANK
MAX
7
9
CAS Latency
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T3
NOP
t LZ
40
SYMBOL* tRAS tOH tHZ(3) tCMS tRCD tRC tCMH tLZ tHZ(2) tRP
T4
NOP
DOUT m
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
t OH
AC
MIN
2.5
24 20 80 50 1 2 1 -8 80,000
T5
NOP
MAX
DOUT m+1
7
6
t OH
AC
MIN
2.5
60
30 30 90 1 3 1 -10
T6
DOUT m+2
NOP
80,000
MAX
10
tAC
t OH
8
t RP
UNITS
AS4SD4M16
ns
ns
ns
ns
ns
ns
ns
ns ns ns
T7
NOP
DOUT m+3
tHZ
SDRAM
t OH
BANK
ROW
ROW
ACTIVE
T8
Undefined Don't Care
4321 4321 4321
321 321 321 321 321 321
4321 4321 4321 4321 4321 4321
4321 4321 4321 4321 4321 4321
321 321 321 321 321 321
321 321 321 321 321 321
87654321 87654321 87654321 87654321 87654321 87654321
t AC
5432321 4121 3 5432121 43 5432321 41 5432321 41 3 5432321 4121
3210987654321 3210987654321 3210987654321 3210987654321 3210987654321
t AC t AC
4321 7 4 7654321321 4321654321321 4 4321654321321 7 4 4327 4321654321321 1 4 1 4321 4321654324321 7
t AC t AC
43210987654321 43210987654321 43210987654321 43210987654321 43210987654321
4321 7 1 4 7654324321 4321654321321 1 1 4327654324321 7 4327654321321 321 1 4 1 4321 4321654324321
54321 54321 54321 54321 54321
6541 5654321 432 5432321 4321 5654321 1 5654321 4321 6543 5432121 2132111 4 32 2 24 32 213222 12 2132111 4 311 21 12 4 22 2 1 2132111 2132311 43 654321 654321 654321 654321 654321
6543214321 65 54324 6553211 44324 65 6553211321 44321321 65 6543211321 44324 65 6553211321 54324 65
654321321 654 5432 6553211 44323 654 655321121 4432321 654 654321121 44321 654 655321121 54323 6543
654321321 654 54323 6553211 44323 654 655321121 4432121 654 654432121 44323 654 655321121 53213 654
765432121 76543 54321 7654321 76543 765432121 5432121 76543 765432121 54321 76543 765432121 76543
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
214 221 321 321 2 52 2143211 3513321 2543211 351 31 22 2113311 314 221 22 2143211 351 321 22
313 321 223 321 23 4 3412321 2112121 323 3 243 121 2 43 13 311 321 2212121 3412121 2132121 3
2412321 321 321 2 43 2132121 313 321 241 121 341 3 23 3 2132121 313 321 21 2112321 3232121 4
213 321 321 321 2 43 2132121 3412321 2432121 341 1 23 2112121 313 321 23 2132121 341 321 23
2412321 321 321 2 43 2132121 313 321 241 121 341 3 23 3 2132121 313 321 21 2112321 3232121 4
313 21 223 21 22 4 341221 211211 313 2 223 11 22 42 343 21 211211 321211 211211 42
313 11 223 21 22 4 341221 211221 1 313 2 223 11 21 42 343 21 211221 321211 211221 4
t CH
311 21 223 21 2 41 341221 213221 321 1 241 21 2 41 11 311 21 223221 343221 213221 1
313 11 221 21 2 42 343221 211221 323 2 243 11 21 41 12 311 21 221221 341211 213221
t CK
654321 654321 654321 654321 654321
COMMAND
CKE
CLK
t CKS t CKH
t CMS t CMH
Austin Semiconductor, Inc.
ACTIVE
T0
NOP
T1
ALTERNATING BANK READ ACCESSES1
t CMS
t
CL
READ
T2
t CMH
313 3 2412121 2 4 313 2232321 2 341 321 2112121 313 3 221 121 2 43 3412121 2132121
NOP
2132121 341 31 22 243231 31 2 2 2132121 341 311 21 22 2132111 323 21 23 2 2112321 341 12 41
READ
2132121 4 31 2 24 31 213222 12 2132121 4 311 21 12 4 31 2 3 2132111 2132121 42
NOP
2132111 4 22 3 24 32 213222 13 2132211 4 111 21 12 4 32 1 3 2132211 2132211 41
323 31 2112121 42 34 2 213231 2 341 311 2112121 23 22 343 31 213 12 22 2 3212111 2112121 43
NOP
213221 4 31 24 31 213221 12 213221 4 311 21 221 4 32 213311 213221 41
8765432109876554321 5432 4321 5432 8765432109876554321 43211 8765432109876543211 8765432109876554321 5432 4321 8765432109876543211 54321
DQM / DQML, DQMH
A0-A9, A11
t AS
t AS
ROW
t AH
t AH
ENABLE AUTO PRECHARGE
5432321 6541 4321 5432321 6541 5654321 5654321 4321 5654321 4321
6543311121 842223 7354 6 65443113 82124 3254 76 6544321121 82112121 32223 765 6544211121 822513 3354 7 6542112121 831223 46 4 76
542115432121 326 6543 87 1 5482 7654323 2 7 74 4 23 3 6 42 1 41 765653321 54811565332121 211 765532121 326 74521 6 42 1 4 54811565332121 226 7655321 37 74 4 23 6 44 1 41 54211565332121 326 74523 87 6 4 2 1
654322121 54313 7654 6554321 43221 74323 654 4 655432121 4321121 76513 655431121 46523 74 4 654322121 53221 76513
54271543221 87 32 54331 2 81665421 54276654311 32 82 65431 54276543221 31154322 1 811 21 54216543211 21165421 32 54876654321 321 32
321 321 321 321 321
BA0, BA1
A10
DQ
t AS
BANK 0
ROW
t AH
t RAS - BANK 0
4321 4321 3 21 321 321 321
NOTE:
AS4SD4M16 Rev. 1.5 10/01
1. For this example, the burst length = 4, the CAS latency = 2. 2. x16: A8, A9 and A11 = "Don't Care."
TIMING PARAMETERS
* CAS latency indicated in parentheseses.
SYMBOL*
tAH
tAC(2)
tAC(3)
tCK(2)
tCK(3)
tCL
tCH
tAS
tCKH
tCKS
t RC - BANK 0
MIN
t RCD - BANK 0
t RRD
12
2
1
8
3
3
2
1
-8
MAX
6.5
9
COLUMN m2
MIN
3.5
3.5
10
15
3
1
3
1
BANK 0
-10
MAX
9
7
CAS Latency - BANK 0
UNITS
T3
t LZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41
ROW ROW
SYMBOL*
BANK 4
tRAS
tCMH
tRRD
tRP
tRCD
tRC
tOH
tLZ
tCMS
ACTIVE
T4
DOUT m
t OH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
RCD - BANK 1
MIN
2.5
20 24 20 80 50 1 2 1
T5
DOUT m+1
ENABLE AUTO PRECHARGE
-8
t OH
80,000
MAX
COLUMN b2
BANK 4
T6
DOUT m+2
MIN
2.5
60
20 30 30 90 1 3 1
t OH
CAS Latency - BANK 1
t RP - BANK 0
-10
80,000
MAX
T7
DOUT m+3
AS4SD4M16
t OH
UNITS
SDRAM
ns
ns
ns
ns
ns
ns ns ns ns
ROW
ROW
BANK 0
T8
ACTIVE
t RCD - BANK 0
DOUT b
t AC
t OH
Undefined Don't Care
54 1 54321 54321 54321 32
321 321 321
t HZ
10987654321098765432121098765432109876543210987656543 4321 65432654321 7651321 4 1098765432109876543212109876543210987654321098765432321 6541 65765432 4326 1 1098765432109876543212109876543210987654321098765432321 654121 65432454321 765632121 41 1543 1098765432109876543212109876543210987654321098765432121 6543 65765132321 4326541 1098765432109876543212109876543210987654321098765432121 6543 65432654321 7651321 4 25 6 41 1 614321210987654321098765432109876543212109876543210987654321098765654321 43221 25432121098765432109876543210987654321210987654321098765432109876563221 214321210987654321098765432109876543212109876543210987654321098765654321 61 5 454211 3232 1 214321210987654321098765432109876543212109876543210987654321098765654211 65 43221 1 214321210987654321098765432109876543212109876543210987654321098765654321 65 43232 1 1098765432109876543212109876543210987654321098765654321 432 6541 1098765432109876543212109876543210987654321098765432321 1 1098765432109876543212109876543210987654321098765432121 6543 1098765432109876543212109876543210987654321098765432121 6543 3 4 1321 1210987654324321 3210987654321321 1 3210987654321321 4 1 1210987654321321 3 4 4321 321 321 321 321 321
NOP NOP
COLUMN
321 321 321 321 321 321 321 321 321 321 321 321 321 321
543216541 765432 54321654321 765432321 54321654321 7654321 1 54321654321 7654321
21 21 21 21 21
21 21 21 21 21
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
21 21 21 21 21
21 21 21 21 21
211 21 34 2 243211 343 11 22 211211 313211 21 2 213221 341 2 22
21 311 42 21 221 243321 11 4 22 1 32 213221 243311 213211
32 211 21 42 313 1 223211 22 43 2 343221 211221 321 11 211211 4
211 321 32 43 2412121 3412121 23 3 2132121 313 121 23 2112321 323 3 4
32 211 21 42 313 1 223211 22 42 343211 211221 321 11 211221 43
211 21 32 42 241211 341211 23 2 213211 313 11 22 211221 323 2 4
32 211 321 43 313 1 2212121 23 43 3432321 2132321 321 121 2112121 43
21 211 4 32 21 221 243321 11 42 1 32 213221 213311 243211
321221 213 1 4 321221 213 21 4 11 43 2 321211 221 21 343221 21 1
t CH CK
3212121 33 3212121 21 321 23 321 1 3 11 3232321 3212121
CL
COMMAND ACTIVE
54321 54321 54321 54321
CKE
CLK
t CKS t CKH
t CMS t CMH
T0
Austin Semiconductor, Inc.
t
NOP
T1
t CMS
t
READ
T2
t CMH
323 2 4 21 41211 313 2 223221 2 341 11 21122 323 21 211 11 42 321211
341 3 22 213211 2432111 343 211 2 32 2 311 32 21 1 2112321 2112211 32 22 4 323 11
21 32 4 43211 21 321 243211 1 32 213211 1 21 221 4 32 213321
213211 42 24 2 213221 1 4 11 243221 11 2 213211 213211 42
321211 4 223 2 1 34 21322 311 11 22 41 21 22322 341 11 213211 321211 43 2
243211 1 22 3 24 311 243221 1 1 32 213221 12 1 213311 4 32 243211
76543210987654652321 5432 1 4 42 3 41 5653321 76543210987655653321 4652321 3 41 1 76543210987654652321 4 42 3 41 76543210987655653321 5432 1 4321 1 4 42 3 41 1 76543210987654652321
321 321 321 321 321
BA0, BA1
DQM / DQML, DQMH
A0-A9, A11
A10
t AS
t AS
t AS
BANK
ROW
ROW
t AH
t AH
t AH
BANK
m2
READ -- FULL-PAGE BURST1
T3
NOP
t AC
T4
NOP
t AC
tOH
T5
NOP
t AC
t OH
T6
NOP
t AC
t OH
Tn+1
NOP
t AC
t OH
Tn+2
BURST TERM
AS4SD4M16
t AC
t OH
21 2 1 21 11 21 21 21
321 321 321 321 321 321
321 321 321 321 321 321
321 321 321 321 321 321
321 321 321 321 321 321
321 321 321 321 321 321
87654321 87654321 87654321 87654321 87654321 87654321
NOTE:
AS4SD4M16 Rev. 1.5 10/01
1. For this example, the CAS latency = 2. 2. x16: A8, A9 and A11 = "Don't Care." 3. Page left open, no tRP.
DQ
TIMING PARAMETERS
* CAS latency indicated in parentheseses.
SYMBOL*
tAH
tAC(2)
tAC(3)
tCKH
tCK(2)
tCK(3)
tCL
tCH
tAS
tCKS
t RCD
MIN
12
2
1
8
3
3
2
1
-8
MAX
6.5
9
MIN
3.5
3.5
15
10
3
1
3
1
CAS Latency
-10
MAX
9
7
t LZ
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
42
DOUT m
256 (x16) locations within same row.
SYMBOL*
tLZ
tHZ(2)
tRCD
tCMH
tOH
tHZ(3)
tCMS
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
DOUT m+1
Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command.
MIN
2.5 1 2 1 -8
DOUTm+2
20 MAX 7 6
Full page completed.
MIN
2.5 1 3 1
DOUT m-1
30 -10 MAX 10 8
UNITS
DOUT m
ns ns ns ns ns ns ns
SDRAM
Tn+3
DOUT m+1
t OH
Undefined Don't Care
Tn+4
432 4321 4321 4321 1
21 21 21 21 21 21 21 21 21
4321 4321 4321 4321 4321 4321 4321
987654321 987654321 987654321 987654321 987654321 987654321 987654321
t AC
21 21 21 21 21 21 21 21 21
87654321 87654321 87654321 87654321 87654321 87654321 87654321
t AC
8765432109876543212109876543210987654321098765654121 4323 1 8765432109876543212109876543210987654321098765432321 654 8765432109876543212109876543210987654321098765432121 6543 8765432109876543212109876543210987654321098765432121 6543 654321
7654327654 1 7657657654321 4324321 1 4321321 7657657654321 4327654 1 7657654321321 4324321 1 7657657654321 4321 1 7654327654321
321 321 321 321 321
21 651321 4 7 321 1 26 7654321098765432121098765432109876543210987654654 2154321098765432121098765432109876543210987654321321 7154321098765432121098765432109876543210987654321321 6 654 26 7154321098765432121098765432109876543210987654321321 651 4 2154321098765432121098765432109876543210987654321321 76 651 4
6543217654321 2 1 81 1 65432176543 87654321 27654321 1 6543217654321 8765432121 21 6548765432121 87654323 32176541 21 1 1 6543217654321 21 6543217654321 87654321 6547654324321 87654321 6543217654321 83217651 6587654321321 43217654 87654321 6543217654321
321 321 321 321 321 321 321 321 321 321
7654 87654321098765432121098765432109876543210987654321321 87654321098765432121098765432109876543210987654321321 7654 87654321098765432121098765432109876543210987654321321 7654 87654321098765432121098765432109876543210987654321321 7654 87654321098765432121098765432109876543210987654321321 7654 298765432109876543210987654324321 0 4 1321 018765432109876543210987654324321 29 1 21 018765432109876543210987654324321 9 1 018765432109876543210987654321321 9 29 4 4 218765432109876543210987654321321 0 4321 654321 654321 654321 654321 654321 21 21 21 21 21 321 321 321 321 321 321 321 321 321 321
NOP NOP NOP NOP
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
32 3 21 3 4 323 121 2112321 41 41 121 31323 2232121 23 3 343 321 211 321 3212121 2112321 4
214 321 32 22 21 5 2113221 351 311 2513221 3543221 24 2 2113311 311 321 21 2143211 354 32 2
32 21 32 52 1 324 211 2113321 5 51 311 314322 2243211 2 2 354 321 211 321 3213211 2113221 54
321 21 21 2 42 3213211 4 4 11 3213211 21 21 243221 12 3213211 3213211 42 2
211 121 32 3 23 4 2112121 343 321 2412321 3432121 23 3 2132121 311 321 23 2112321 323 1 4
32 3 21 3 4 323 321 2112121 4 41 121 31323 2232321 23 3 343 321 211 121 3212121 2112121 43
32 21 51 1 324 221 2113321 5 51 321 314321 2243221 24 21 354 221 211 321 3213321 2113321 51
t CH
321 11 21 2 42 3213221 41 4 21 3213221 21 11 243221 1 3213211 3243211 12 2
211 321 34 3 2 2132321 341 121 21 2132321 3432321 23 2432121 311 121 21 1 2132321 341 3 2
t CKH t CK
654321 654321 654321 654321 654321
t CKS
COMMAND
CKE
CLK
t CMS t CMH
ACTIVE
Austin Semiconductor, Inc.
T0
NOP
T1
t CMS
t
CL
READ
T2
t CMH
21 2 21 12 43 432211 213212 3 2132111 4 211 32 24 32 2132211 1 12 1 2132211 43
NOP
654321 654321 654321 654321 654321
NOP
654321 654321 654321 654321 654321
987654321098765654321 65432 432121 543 987654321098765432121 4543 321 987654321098765654321 6543 987654321098765654321 4321 1 987654321098765432121
BA0, BA1
DQM / DQML, DQMH
A0-A9, A11
A10
DQ
t AS
t AS
t AS
BANK
ROW
ROW
t AH
t AH
t AH
t RCD
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN m2
READ -- DQM OPERATION1
BANK
CAS Latency
41 3321 2 321 321
t HZ t LZ t HZ
NOTE:
AS4SD4M16 Rev. 1.5 10/01
1. For this example, the burst length = 4 , the CAS latency = 2. 2. x16: A8, A9 and A11 = "Don't Care." * CAS latency indicated in parentheseses.
TIMING PARAMETERS
SYMBOL*
tAC(3)
tAC(2)
tCKH
tAH
tCK(2)
tCK(3)
tCL
tCH
tAS
tCKS
MIN
12
2
1
8
3
3
2
1
-8
MAX
6.5
9
MIN
3.5
3.5
10
15
3
1
3
1
-10
MAX
7
9
UNITS
T3
t LZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43
SYMBOL* tRCD tCMH tOH tHZ(3) tCMS tLZ tHZ(2)
T4
DOUT m
t OH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MIN
2.5 1 2 1
20
T5
-8
MAX
7
6
T6
MIN
2.5
30
DOUT m+2
1
3
1
t AC
t OH
-10
MAX
10
8
T7
AS4SD4M16
DOUT m+3
UNITS
ns ns ns ns ns ns
t OH
ns
SDRAM
T8
Undefined Don't Care
4321 4321
4321 4321 3 21 321 321 321
t RAS t RC
16543210987654321098765452121 7 341 23 1 76543210987654321098765432121 1 543 4 76543210987654321098765432121 1 523 76543210987654321098765432121 1 543 43 16543210987654321098765432121 7 521 6543 5654121 4321 5432321 5432321 6541 5432121 6543 5432121 6543 65654321 7 654321 76543 654 65432121 5432121 74323 65432121 76543 3 65432121 76541
BANK BANK
321 321 321 321 321
t
21 21 21 21 21
t
321 321 321 321 321
t
6546543210987654321 7321 654 7321 6543213210987654321 7654 6546543210987654321 7 6576543210987654321 4321 6543213210987654321 65432654321 1 7651321 4 65465132321 7656321 4 65432654321 7324541 65765132121 4324543 7656321 4 1 65432654321
BANK
t
654321 654321 7 654326543210987654321 76 654 654321543210987654321321 71543210987654321321 6 654 654321543210987654321321 76 654 654321543210987654321321 76 654
4321 4321 4321 4321 4321
5654321 4321 5432321 6541 5432321 6541 5432121 6543 5432121 6543 5654321 4321 5432321 6541 5432321 6541 5432121 6543 5432121 6543
65432121 54321 76543 65432121 54323 7654 65432121 76543 65432121 54321 76543 3 65432121 54321 76541
654876543210987654543 9 9876543210987654321 321 932154321098765432121 65987654321098765432321 4876 541 65932154321098765432321 4321 876 541 65932154321098765432121 4876543210987654323 541 65932154321098765432321 4876543210987654541 9876 9876 321
4321 4321 432765654321 1 1 4327 6543 432165432121 1 1 4321 1 432765654321 4327 4323 4321 6541 1 1 1 1 432165432121 432765654321
321 321 321 321 321 321 321 321 321 321
6543219876543210987654321098765654321 210 4321 6542109876543210987654321098765432321 3 6541 6542219876543210987654321098765432321 321 10 6541 6542219876543210987654321098765432121 310 6541 6543219876543210987654321098765654321 210 4323 21 31 3213221 24321213243211 12 4 1 32 4 21323 2 2 21321213213211 4 121324 311 31 1 32 21 24 31 324 321 21321213213211 1 11 1 31 2 21323213213221 42 42 21 21 21 21 21 21 21 21 21 21
NOP NOP
76547656541 8 432 8321432321 7654765654321 43216541 7658765432321 83214321 7654765432121 43216543 321 1 7658765654321
654321 654321 654321 654321 654321
321 321 321 321 321
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
4321 4321 4321 4321 4321
324 11 21 2 11 42 3213221 43221 3243221 21 21 21 11 11 2 3213211 3213221 4
324 11 21 2 11 42 3213221 43221 3243221 21 11 21 21 11 3213221 3213221 41
324 21 21 2 12 4 3213211 43211 3243211 21 21 21 21 12 2 3213211 3213211 42
31 3 223 3 2 4 343 321 2112121 412121 313 3 2232121 23 3 343 321 2112321 321 121 2112121 4
2432121 323 3 2 43 2112121 311 321 2412121 343 321 23 2112121 313 121 23 2112321 323 3 4
241211 321 2 2 42 213211 313 21 241211 343 21 22 213211 311 11 22 211221 323 2 4
2412121 321 3 2 43 2132121 313 321 2412121 343 321 23 2132121 311 121 23 2112321 323 3 4
t CH
211 3 34 1 2 2432121 3132321 41 121 23 2132321 313 321 2 2412121 341 321 23 2132321 321 1
31 221 3 2 4 343 121 2112321 432121 31 1 2232121 2 341 121 2132321 321 321 2112321 43
t CK
654321 654321 654321 654321 654321
COMMAND
CKE
CLK
t CKS t CKH
t CMS t CMH
Austin Semiconductor, Inc.
ACTIVE
T0
NOP
T1
WRITE -- WITHOUT AUTO PRECHARGE1
t CMS
t
CL
WRITE
T2
t CMH
18765432109876543210987654324321 9 1321 98765432109876543210987654324321 1 1 1 98765432109876543210987654324321 1 98765432109876543210987654321321 1 4 18765432109876543210987654321321 9 4321
NOP
PRECHARGE
21 21 21 32 4 432111 213232 2 3 2132121 4 111 2 24 22 2132111 1 31 2 2132321 41
98765432109876554321 5432 5432 43211 98765432109876543211 4321 98765432109876554321 5432 5432 98765432109876554321 43211 98765432109876543211
NOTE:
AS4SD4M16 Rev. 1.5 10/01
* CAS latency indicated in parentheseses. 1. For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns are required between and the PRECHARGE command, regardless of frequency. 3. x16: A8, A9 and A11 = "Don't Care."
BA0, BA1
DQM / DQML, DQMH
A0-A9, A11
A10
DQ
TIMING PARAMETERS
SYMBOL*
tCKH
tCK(2)
tCK(3)
tCL
tCH
tAS
tAC(3)
tAH
tAC(2)
tCKS
t AS
t AS
t AS
ROW
ROW
t AH
t AH
t AH
t RCD
MIN
12
2
1
8
3
3
2
1
-8
MAX
6.5
9
DISABLE AUTO PRECHARGE
MIN
3.5
3.5
10
15
3
1
3
1
DS
-10
DIN m
BANK
COLUMN
t
MAX
DH
7
9
m2
UNITS
DS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIN m+1
T3
t
DH
44
SYMBOL* tRAS tDS tDH tCMS tCMH tWR tRP tRCD tRC
DS
DIN m+2
T4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
t
DH
MIN
15 24 20 80 50 2 1 2 1
DS
DIN m+3
-8
T5
80,000
MAX
t
DH
t WR2
SINGLE BANK
ALL BANKS
MIN
60
15 30 30 90 3 1 3 1
T6
-10
80,000
MAX
t RP
UNITS
AS4SD4M16
T7
NOP
ns
ns
ns
ns
ns
ns ns ns ns
SDRAM
ROW
ROW
ACTIVE
T8
Undefined Don't Care
4321 2 4321 4321 4321 31
321 321
1 543 3 2 1 54121 2109876543210987654321098765432121 11098765432109876543210987654321 543 2109876543210987654321098765432121 1109876543210987654321098765432121 2 543 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321
BANK
321 321 321 321
t
21 21 21 21
t
21 21 21 21
t
654321210987654321 6543 654321210987654321 6543 656543210987654321 4321 6543 654321210987654321 65432351 65462 1 3 654624321 65432654321 1 65454324321 632151 31 654621 65654121321 432354 1 65432654321 54721432121 1 7 3654321 1 54365654321 1216543 54365432121 1 7 3214323 1 1 54765654321 1216541
BANK
t
654365 7 543 72143212109876543210987654321098765432121 65436543212109876543210987654321098765432121 543 65472143212109876543210987654321098765432121 765 321 65 543 65432143212109876543210987654321098765432121 543 65432143212109876543210987654321098765432121 765 543
4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321
654765 8 4321 6543 832143212109876543210987654321098765654321 65476543212109876543210987654321098765432121 65832143212109876543210987654321098765432321 8765 4321 765 6541 65432143212109876543210987654321098765432121 6543 65432143212109876543210987654321098765432121 8765 6543 321 311 3243221 12 4 3213221 1 321 321 4 31 3213211 3213221 4 32 321 21 21 21 21 21 21 31 21 221 42 213221 43311 21 221 4 32 213311 213221 41 321 321 321 321 321
NOP
657654324321 4321651 32 657654651321 4321651 657654324321 4321324 657654321321 4321 1 657654654321 4321654
7654321 7654321 7654321 7654321 7654321
21 21 21 21 21
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
313 21 243 11 12 4 321221 221221 321221 213 2 41 11 321211 243 21 42 321211 213 21
3 223 321 3 3112321 2132121 21 321 32 3 221 121 3 323 321 2112121 3 3132121 2112121 33
241221 321 21 2 42 213211 313 21 241 11 341 2 22 2 213211 313 21 21 211221 323211 4
323 21 211 321 3212321 2132121 32 3 211 121 3 323 321 2112121 3232121 2112121 3
2412321 321 321 2 43 2132121 313 321 241 121 341 3 23 3 2132121 313 321 23 2112121 3232121 4
21 11 21 21 12 4 243221 213221 1 21 11 42 12 1 24 21 213221 213211 213221 4
313 11 223 21 22 4 341221 211221 1 313 2 223 11 21 42 343 21 211221 321211 211221 4
21 21 21 21 1 41 243221 213221 1 24 21 41 12 21 21 213221 12 213211 243211
t CH
313 1 21 243 32 1 4 1 31 3212321 2212321 3 3212121 213 1 2 1 43 1 12 3 3212321 221 3 2 1 43 3432121 213 3 2 1
t CL
211 21 341 11 22 213221 343221 21 213221 341 2 21 243211 311 11 22 213221 341 21 2
t CK
654321 654321 654321 654321 654321
COMMAND
DQM / DQML, DQMH
CKE
CLK
t CKS t CKH
t CMS t CMH
ACTIVE
Austin Semiconductor, Inc.
T0
NOP
T1
WRITE -- WITH AUTO PRECHARGE1
t CMS
WRITE
T2
t CMH
1 3 43 3 1212109876543210987654321098765432121 3212109876543210987654321098765432121 4321 1 3212109876543210987654321098765432121 43 3 1212109876543210987654321098765432121 3 4321
NOP NOP NOP
ACTIVE
24 2321 21 3321 1 21 2 1 2132321 433321 1 21 2321 4 11 1 31 1 2 2133321 2432321 21
8765432109876554321 5432 5432 43211 8765432109876543211 8765432109876554321 5432 4321 8765432109876543211 54321
A0-A9, A11
t AS
t AS
ROW
t AH
t AH
ENABLE AUTO PRECHARGE
6543098765432121098765432109876543210987654321 109 109 32 321 654121876543212109876543210987654321098765454321 321876543212109876543210987654321098765454321 1 654121876543212109876543210987654321098765454321 1098765432121098765432109876543210987654321 3098765432121098765432109876543210987654321 321 321 654321876543212109876543210987654321098765454321 109 109
m2
NOTE:
AS4SD4M16 Rev. 1.5 10/01
BA0, BA1
1. For this example, the burst length = 4, i.e., two-clock minimum for tWR. 2. x16: A8, A9 and A11 = "Don't Care."
A10
DQ
TIMING PARAMETERS
* CAS latency indicated in parentheseses.
SYMBOL*
tCKH
tAH
tCMS
tCMH
tCKS
tCK(2)
tCK(3)
tCL
tCH
tAS
t AS
ROW
t AH
t RCD t RAS
t RC
MIN
12
2
1
2
1
8
3
3
2
1
-8
MAX
MIN
3.5
3.5
10
15
3
1
3
1
3
1
DS
DIN m
BANK
-10
COLUMN
t
DH
MAX
DS
DIN m+1
T3
UNITS
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DH
45
DS
DIN m+2
T4
NOP
SYMBOL*
tDH
tWR
tRP
tRCD
tRC
tRAS
tDS
t
DH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
DS
DIN m+3
T5
NOP
1 CLK+ 8ns MIN 24 20 80 50
t
2
1
DH
t WR2
-8
80,000
MAX
T6
1 CLK+ 8ns MIN 60 30 30 90 3 1
T7
-10
80,000
MAX
t RP
AS4SD4M16
T8
SDRAM
UNITS
ns
ns ns ns ns ns
ns
ROW
ROW
T9
Undefined Don't Care
321 321 321 321
21 21 21 21
t
21 21 21 21
t
21 21 21 21
t
5 4321 54321321 4324321 4 54321321 4 54321321 1 4 54324321 4 1321 654321 654321 654321 654321
09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 09876543210987654321 6543211 54323 7654 6553211210987654321 44321210987654321 76543 6553211210987654321 44321 76543 6554321210987654321 43211 76543
654321 654321 654321 654321 654321
654321 654321 6543210987654321321 4 654 6543210987654321321 4321 321 654 6543210987654321321 654 6543210987654321321 654 21 321 243211 12 42 213221 3 213211 4 31 24 321 213221 1 31 213211 42 321 321 321 321
7654321 7654321 7654321 7654321
21 21 21 21
321 321 321 321
21 21 21 21
321 321 321 321
21 21 21 21
321 321 321 321
321 321 321 321
21 21 21 21
321 321 321 321
21 211 1 32 4 3213221 243321 1 3213221 24 321 41 12 3243211 21 321 1 32 3213211
323 321 2 41 3 3412321 2132121 32 3 241 121 23 3 313 321 2412121 3132121 2112121 23 3 4
21 21 12 4 243221 213211 21 11 41 12 2 24 21 213211 213211 213221 42
321 321 23 3 4 3412321 2132121 31 3 221 121 23 43 343 321 2112121 3232121 2112121 43 3
323 321 2 41 3 2132121 3412321 241 121 341 3 23 3 2132121 313 321 23 2112121 3232121 4
321221 42 321221 213 11 43 1 321 21 24 2 41 12 321211 213 11 321221 213221 43
323 321 23 3 4 3412321 2112121 313 3 223 121 23 43 343 321 2112121 3212121 2112121 43
323 21 2 41 1 341221 213221 321 2 243 21 21 41 12 311 21 223221 311211 243211
t CH
24 32 1 3213221 243321 1 211 321 321 21 321 41 11 3213221 243221 1 3213321 4 21
CL
341 121 23 2132321 3432321 21 1 2132321 341 3 21 2432121 311 121 23 2132321 341 321 2
t CK
54321 54321 54321 54321 54321
COMMAND
CKE
CLK
t CKS t CKH
t CMS t CMH
ACTIVE
Austin Semiconductor, Inc.
T0
NOP
T1
t CMS
t
ALTERNATING BANK WRITE ACCESSES1
WRITE
T2
t CMH
321 2 321 311 4 43221 3213211 1 31 3243221 4 32 321 321 3243211 1 32 2 3213211
21 321 243211 12 42 213221 3 213211 4 31 24 321 213211 1 32 213211 42
323 321 2112121 321 3 2132321 321 1 2132121 323 3 2132321 321 121 2112121
NOTES: 1. For this example, the burst length = 4, i.e., two-clock minimum for tWR. 2. Requires once clock plus time (8ns) with AUTO PRECHARGE or 15ns with PRECHARGE. 3. x16: A8, A9 and A11 = "Don't Care."
321 321 321 321 321
t DS
321 321 321 321 321
t
321 321 321 321 321
t
21 21 21 21 21
t
654321210987654321 76543 654321210987654321 76543 654321210987654321 76543 676543210987654321 54321 76543 654321210987654321 432165432321 7 1 4327 432165432321 1 3 1 432765432321 7 1 121 432165432321 321 1 4321 432165432321 7 1 5422 7 36 2 1 54265654321 71165411 311432321 2543221 54215432121 26165431 72 32 2 54765654321 31143211 2
BANK 0 t
3211654321321 4327 3 421 3327654321211 4 3 4 3217654321321 4211 321 321 432 3217654321211 4327 3 4 3211654321321 4321 321 432 541655454 3 7 6 547215321121 1214322121 36544323 6313 54 547215321121 16543213 3 651 1 4 541215432121 36544313 7 652 4
43210987654321 43210987654321 43210987654321 43210987654321 43210987654321 6573221 5431 43221 2 655654321 7654321 44311 657654321 73221 44321 2 1 655654321 53221 44311
4321 4321 4321 4321 4321 321 321 321 321
654321321 654 654321 4654 654 654321321 4321321 321 654321321 654 654321321 654 21 311 243221 12 4 213221 31 213221 4 31 24 321 213221 1 31 213211 42
654654321 54321 43211 432 321 655654321 432 655654321 44321 321 654654321 53211
65432321 432 6541 65432121 4321 6543 1 65654321 4321 65432121 4321 6543 65654321
321 321 321 321 321
21 21 243211 12 42 213221 213211 41 24 21 213221 11 213211 42
321 321 3243211 12 42 3213221 3 3213211 4 31 324 321 3213211 1 32 3213211 42
21 321 243221 11 4 22 213321 11 243221 4 31 21 221 213311 1 32 243211
8765432109876544321 65432 543 432 321 632121 87654321098765432111 44321 87654321098765643221 65432 543 87654321098765643221 45431 321 87654321098765432111
AS4SD4M16 Rev. 1.5 10/01
BA0, BA1
Undefined
Don't Care
DQM / DQML, DQMH
A0-A9, A11
A10
DQ
* CAS latency indicated in parentheseses.
TIMING PARAMETERS
SYMBOL*
t AS
t AS
t AS
tCKH
tAH
tCMS
tCMH
tCKS
tCK(2)
tCK(3)
tCL
tCH
tAS
ROW
ROW
t AH
t AH
t AH
t RC - BANK 0 t RRD
t RCD - BANK 0 t RAS - BANK 0
MIN
12
2
1
2
1
8
3
3
2
1
-8
ENABLE AUTO PRECHARGE
MAX
COLUMN
BANK 0
m3
DS
MIN
DIN m
3.5
3.5
15
10
3
1
3
1
3
1
t
DH
-10
MAX
DS
T3
DIN m+1
NOP
UNITS
t
DH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ROW
ROW
46
ACTIVE
DS BANK 1
DIN m+2
T4
SYMBOL*
tWR
tRRD
tRP
tRCD
tRC
tDH
tRAS
tDS
t
DH
t RCD - BANK 1
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
DS
T5
NOP
DIN m+3
1 CLK+ 8ns MIN 20 24 20 80 50 2 1
t DH COLUMN b3
ENABLE AUTO PRECHARGE
t WR - BANK 0
-8
80,000
WRITE
MAX
BANK 1
T6
DIN b
t
DH
1 CLK+ 8ns MIN 60 20 30 30 90 2 1 -10
NOP
DS
T7
DIN b+1
80,000
MAX
tDH
t RP - BANK 0
AS4SD4M16
UNITS
DS
NOP
T8
ns
ns ns ns ns ns ns ns
54321 54321 54321
DIN b+2
SDRAM
t DH
ACTIVE
DS
BANK 0
T9
ROW
ROW
DIN b+3
tRCD - BANK 0
t
WR - BANK 1 t DH
54 1 43321 2 4321 4321
4321 4321
4321 44321 3 21 4321 4321 4321
98765432156543221 67 1 98765432154321221 676543 1 98765432174321 1 6 4323 654 98765432154321221 654321221 74321 1 6543 98765432154321221 676541 1 6543 3 98765432154321221 674321 1
t DS t DH
321 321 321 321 321 321
321 321 321 321 321 321
t
321 321 321 321 321 321
t
432109876543212109876543210987654321098765654321 4321 432109876543212109876543210987654321098765432321 6541 432109876543212109876543210987654321098765432321 6541 432109876543212109876543210987654321098765432121 6543 432109876543212109876543210987654321098765432121 6543
1 654321 21 3 54321 21 1 3212109876543210987654321098765432121098765432109876543210987665432 54321 12121098765432109876543210987654321210987654321098765432109876543211 32121098765432109876543210987654321210987654321098765432109876654321 1 32121098765432109876543210987654321210987654321098765432109876543211 54332 65421 21 21 12121098765432109876543210987654321210987654321098765432109876654321 3 432109876543212109876543210987654321098765654121 4321 6543 432109876543212109876543210987654321098765432321 432109876543212109876543210987654321098765432321 6541 432109876543212109876543210987654321098765432321 6541 432109876543212109876543210987654321098765432121 6543 432109876543212109876543210987654321098765432121 6543 217654321321 8 4 287654321321 1 4 287654321321 1 4 4321 287654321321 1 4 217654321321 8 4 21 21 21 21 21
BURST TERM
NOP COLUMN
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
21 21 21 21 21
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
4321 4321 4321 4321 4321
351 221 2 51 2 3113321 24 31 2243211 35 21 3213221 21 2 54 321 254 321 1 31 3113221 2543211 2143211 2
21 3 4 2132121 13 43 32432321 321 121 2132121 13 4 321 3 32432121 21 321 32132121 32132121 43
321 2 4 3213211 12 42 3243221 321 11 3213211 12 4 21 2 321 21 3243211 3213211 3213221 41
32 52 3113211 24 32 54 321 2213211 35 21 2 3113211 24 32 54 321 2 224 321 3513211 2113211 2143211 52
321 2 4 3213211 12 42 3243221 321 11 3213211 12 4 21 2 321 21 3243211 3213211 3213221 41
32 52 3113211 24 32 54 321 2213211 35 21 2 3113211 24 32 54 321 2 224 321 3513211 2113211 2143211 52
3212321 41 3 3212321 43 1 213 321 1 3212121 243 321 41 3212321 213 1 1 3212321 43 243 121 2132321
t CH
21 1 1 43 2432321 32132121 321 121 43 2132121 13 4 321 32432321 21 321 32132321 1 32132321 41
t CKH
654321 654321 654321 654321 654321 654321
t CKS
COMMAND
CKE
CLK
t CMS t CMH
Austin Semiconductor, Inc.
ACTIVE
T0
t
CL
T1
NOP
WRITE -- FULL-PAGE BURST
t CMS
t
CK
WRITE
T2
t CMH
321 331 42 432121 321 3 2 43212 321 3311 32432121 1 321 32132111 321 2 3 32132121 4 332
NOP
324 32 2113211 51 35 214322 2 351 311 2113221 24 321 354 31 214322 2 321 311 2113221 5
NOP
21 3 4 432121 21 432121 21 321 2432121 13 2132121 3 2132121 43
NOP
2143211 321 32 4 2113211 32 32 2 2143211 321 321 2143211 324 31 2113221 321 32
NOP
* CAS latency indicated in parentheseses. NOTES: 1. x16: A8, A9 and A11 = "Don't Care." 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open, no t RP.
321 321 321 321 321 321
t
65832143210987654321 8765 4321 65476543210987654321 65876543210987654321 8321 4321 65476543210987654321 65476543210987654321 8321 4321 65876543210987654321 6547 8 83217654321 7654321 65432 6543217651321 47654321 6583217654321 87654324 6587654321321 43217654 1 6543217654321
BANK
t DS
4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321 4321
76543217654321 987654321 76543217654321 987654321 987654321 76543217654321 76543217654321 987654321 987654321 76987654321321 543217654 76543217654321
324 32 2113211 5 35 214321 2 2 351 321 2113211 24 321 354 32 214322 2 321 311 2113211 5
987654321098765487251321 65432 1 56 4 3 6 42 654321 987654321098765487251321 36 4 687453321 987654321098765687453321 487251321 36 4 1 56 4 987654321098765687453321 43212 1 3 6 42 987654321098765487251321 56 4 1
AS4SD4M16 Rev. 1.5 10/01
BA0, BA1
DQM / DQML, DQMH
A0-A9, A11
A10
DQ
TIMING PARAMETERS
SYMBOL*
tCK(2)
tCK(3)
tCL
tCH
tAS
tAH
tCKH
t AS
t AS
t AS
ROW
ROW
t AH
t AH
t AH
t RCD
MIN
12
1
8
3
3
2
1
-8
MAX
MIN
3.5
3.5
10
15
1
3
1
-10
DIN m
MAX
t
BANK
DH
m1
UNITS
ns
ns
ns
ns
ns
ns
ns
DS
DIN m+1
T3
47
t DH
SYMBOL*
tCKS
tRCD
tDS
tDH
tCMS
tCMH
DS
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
DIN m+2
T4
256 (x16) locations within same row.
t
MIN
DH
20 2 1 2 1 2 -8 MAX
DS
Full page completed.
T5
DIN m+3
t
DH
MIN
30 3 1 3 1 3 -10
t DS
Tn+1
MAX
DIN m-1
t
DH
AS4SD4M16
UNITS
ns ns ns ns ns
Full-page burst does not self-terminate. Can use BURST TERMINATE command.2,3
ns
Tn+2
SDRAM
Tn+3
Undefined Don't Care
4321 4321 4321
4321 3 21 321 321 76543210987654765 85 765432109876543214321 8761 765432109876543214321 83214321 761 5 765432109876543214321 8761 5 765432109876543214321 8761 5
321 321 321 321 321
t
76543215 5432 6 765532114321 44325 6 765532114321 443254321 6 765432114321 44321 6 765532114321 54325 65
t
765876543210987654321 94321 765432143210987654321 98765 765432143210987654321 98765 769876543210987654321 54321 98765 765432143210987654321
t DS
2109876543212109876543210987654321098765432121 76543 2109876543212109876543210987654321098765432121 76543 2109876543212109876543210987654321098765432121 76543 2109876543212109876543210987654321098765432121 76543 2109876543212109876543210987654321098765432121 76543 29 0 765 0187654321210987654321098765432109876543214321 2987654321210987654321098765432109876543214321 765 5 2187654321210987654321098765432109876543214321 01 9 761 09 2187654321210987654321098765432109876543214321 765 5 2187654321210987654321098765432109876543214321 09 761
658721 43 7657654321 654321 432 6583217651321 43214321 6587657654321 47654324 6583214321321 4 1 6587657654321 43217654 765437654321 1 8 8217654321 765437654321 1 76548765432321 1 76541 82154321 3217654321 76548767654321 1 321 1 76543217654321 17654321 1
7654 1098765432121098765432109876543210987654321321 1098765432121098765432109876543210987654321321 7654 1098765432121098765432109876543210987654321321 7654 1098765432121098765432109876543210987654321321 7654 1098765432121098765432109876543210987654321321 7654 2109876543210987654324321 1 2109876543210987654321321 4 1 2109876543210987654324321 4321 21 2109876543210987654321321 4 2109876543210987654321321 4
NOP
76543217654321 98765432 76543217654321 987654321 543214321 76987657654321 987654321 76543214321321 543217654 1 76987657654321
654321 654321 654321 654321 654321
321 321 321 321 321
21 21 21 21 21
21 21 21 21 21
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
321 321 321 321 321
2513321 324 21 2 5 2113221 314 321 1 1 2513221 354 321 2 2 2113311 314 221 2 2113221 324 31 5
2412321 321 2 4 2132121 313 321 2412121 341 121 2 2132321 313 321 23 2112121 323 1 4
2513321 324 31 22 5 2113221 314 211 2513221 354 321 21 2113311 314 221 22 2113221 324 31 5
33412321 313 3 221 321 2 4 32132121 32112121 31 3 221 121 23 43 3 33232121 343 321 32112121 43
2513321 324 31 22 5 2143221 311 211 2513221 351 321 21 2143211 314 321 22 2113221 324 31 5
2513221 324 32 2 5 2143211 311 321 2513211 351 311 2 2 2 2143211 314 321 2 2113211 324 32 52
t CH
313 121 243 3 4 1 3212121 2212321 3212321 213 121 4 1 43 3212121 221 321 3432121 21 3
311 221 254 31 5 1 2 3243211 2213321 1 3243221 211 321 5 1 2 5 3213211 224 321 3543211 211 32
t CK
7654321 7654321 7654321 7654321 7654321
t CKS
COMMAND
CLK
CKE
Austin Semiconductor, Inc.
t CMS t CMH
ACTIVE
T0
t CKH
NOP
T1
t CMS
WRITE -- DQM OPERATION1
t
CL
WRITE
T2
t CMH
21 321 51 214332 5 21 2143211 2543221 1 321 5 32 2143211 2143211 5 32
NOP
654321 654321 654321 654321 654321
NOP
654321 654321 654321 654321 654321
10987654321098765432121 6543 10987654321098765432121 6543 4321 10987654321098765654321 6543 6543 1 10987654321098765654321 43212 10987654321098765432121
NOTES: 1. For this example, the burst length = 4. 2. x16: A8, A9 and A11 = "Don't Care."
4321 4321 4321 4321 4321 4321 4321 4321 4321 4321
4321 4321 4321 4321 4321
AS4SD4M16 Rev. 1.5 10/01
BA0, BA1
DQM / DQML, DQMH
A0-A9, A11
* CAS latency indicated in parentheseses.
TIMING PARAMETERS
SYMBOL*
A10
tCKH
tCK(2)
tCK(3)
tCL
tCH
tAS
tAH
DQ
t AS
t AS
t AS
MIN
BANK
12
ROW
1
8
3
3
2
1
ROW
t AH
t AH
t AH
t RCD
-8
MAX
MIN
3.5
3.5
10
15
1
3
1
DISABLE AUTO PRECHARGE
-10
ENABLE AUTO PRECHARGE
MAX
DIN m
COLUMN
BANK
t
DH
UNITS
m2
ns
ns
ns
ns
ns
ns
ns
48
T3
SYMBOL* tCKS tRCD tDS tDH tCMS tCMH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
DS
T4
DIN m+2
MIN
20 2 1 2 1 2
t DH
-8
MAX
DS
T5
NOP
DIN m+3
t
MIN
DH
30 3 1 3 1 3 -10 MAX
T6
AS4SD4M16
SDRAM
UNITS
ns ns ns ns ns ns
T7
NOP
Undefined Don't Care
SDRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS ASI Case #901 (Package Designator DG)
AS4SD4M16
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
49
SDRAM
Austin Semiconductor, Inc.
AS4SD4M16
ORDERING INFORMATION
EXAMPLE: AS4SD4M16DG-10/IT Device Number AS4SD4M16 AS4SD4M16 Package Type DG DG Speed ns -8 -10 Process /* /*
*AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range
-40oC to +85oC -55oC to +125oC
AS4SD4M16 Rev. 1.5 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
50

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